If the NMI line goes from high to low when the RDY is low, is the NMI detected, so that when RDY goes high, NMI is performed ?
Or is the NMI discarded when it occurs when RDY is low ?
(In case of NMI line goes high again before RDY become high)
TL;DR: Yes, it will be detected and performed.
Lets look at the signals:
NMI
- is edge triggered. As soon as a high/low edge comes, the NMI-FF will be set
- Retriggering requires NMI being high again before and during the rising edge of PHI2.
- NMI will not be triggered again unless a new edge comes along after vector pull
- NMI reaction may be delayed up to two cycles
- In any case the actual instruction will always be finished first
- NMI during IRQ handling (before first instruction of IRQ routine) will interrupt after the first instructon is finished.
- Interrupts are always delayed by one instruction when issued during the last cycle of a branch taken within the same page.
- NMI is not delayed during a CLI/SEI/PLP (like INT is)
- NMI (or INT) during a BRK will skip execution of the BRK handling
RDY
- RDY will only be (secure) detected safe when pulled during pase 1
- RDY will not take effect during a write cycle (NMOS only)
- RDY does not affect any other operation beside repeating the actual (memory) cycle
In combination this means:
- NMI detection will happen during RDY
- NMI will start as usual after the actual instruction is finished
- Having RDY applied for one or more times during the actual instruction will not change NMI operation
- Any length of RDY application will not change NMI operation.
Bottom Line: It will work as expected - but there are still many issues to screw up NMI timing.
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So if I understand well, NMI high -> low edge is detected independently of the clock (no matter phi1 or phi2) but the reset of the NMI edge flip-flop is performed on the phi2 ?– JohnmphJan 25 '20 at 14:59
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If a program performs D0 FE (BNE to self) at a page offset less than $FE, could that block interrupts forever? Or would an interrupt which becomes pending just before the first execution of that instruction fire after the second?– supercatJul 8 '21 at 15:37
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@supercat No, AFAIK. When hitting during the last cycle of a branch it will be delayed by one instruction. In this case it will be executed after the next branch.– RaffzahnJul 8 '21 at 15:41
In old 6502 block diagrams, the three hardware interrupts /RST /IRQ /NMI go into an "interrupt logic" block which feeds directly into the instruction decoder, and are not directly influenced by RDY or even Phi2. This tells me that even on original hardware, the edge-trigger circuit for /NMI is asynchronous and that an edge will be detected at any time. This is what you'd expect of an interrupt signal.
On the current-production WDC W65C02S, you can make a stronger assertion, because RDY is physically pulled low by the CPU when a WAI instruction is executed, and is only allowed to go high again when an interrupt is received (any of the three). Thus /NMI must be detected even when RDY is low.
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This is what I expected too but in the following link, it's says that edge is detected during phi2 (Detailed Interrupt Behaviour section) : wiki.nesdev.com/w/index.php/CPU_interrupts– JohnmphJan 25 '20 at 15:02
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Since RDY is sometimes described (including by WDC) as holding the internal state of the CPU in the Phi2 phase, that doesn't preclude very much. Jan 25 '20 at 15:33
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