If the NMI line goes from high to low when the RDY is low, is the NMI detected, so that when RDY goes high, NMI is performed ?
Or is the NMI discarded when it occurs when RDY is low ?
(In case of NMI line goes high again before RDY become high)
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TL;DR: Yes, it will be detected and performed.
Lets look at the signals:
In combination this means:
Bottom Line: It will work as expected - but there are still many issues to screw up NMI timing.
In old 6502 block diagrams, the three hardware interrupts
/RST /IRQ /NMI go into an "interrupt logic" block which feeds directly into the instruction decoder, and are not directly influenced by
RDY or even
Phi2. This tells me that even on original hardware, the edge-trigger circuit for
/NMI is asynchronous and that an edge will be detected at any time. This is what you'd expect of an interrupt signal.
On the current-production WDC W65C02S, you can make a stronger assertion, because
RDY is physically pulled low by the CPU when a
WAI instruction is executed, and is only allowed to go high again when an interrupt is received (any of the three). Thus
/NMI must be detected even when
RDY is low.