The 6502 pinout has a reset pin, which presumably would be used if a reset button is pressed on the machine containing the CPU.

But the 6507 contains the same pin. The 6507 was designed at the request of Atari, to be an extremely stripped-down version of the chip, to save manufacturing cost by eliminating pins that were not absolutely needed; in particular, it can only address 8K of memory. Yet it still has the reset pin.

I conjecture from this that even if the machine does not have a reset button, the supporting circuitry must arrange for reset to be signaled when the power is turned on, in order to signal the CPU to place itself in a known suitable state to start executing code.

Is this correct?

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    You are completely right, almost every single microcontroller and microprocessor has a RESET pin because of this reason. Also, in a reliable system, an external circuit must issue a RESET to stop the CPU from going crazy when the power supply voltage is too low. A bad RESET is often responsible for random failure in embedded systems. See The Least Interesting Circuit in the World for an in-depth discussion of RESET circuit. Commented Jan 28, 2020 at 23:54
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    @比尔盖子, Modern microcontrollers that I work with all have a RESET pin too, but in pretty much every case, you can reliably use the MCU in a design where the RESET is hard-wired to an inactive level. The reason is, they all have power-on-reset controllers built-in to the SOC. Commented Jan 29, 2020 at 17:51
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    @SolomonSlow Most modern microcontrollers also have a brown-out detection circuit internally, no external reset circuits are needed for 95% of applications. but on a few occasions, it may be still advantageous to use an external power-on reset controller. Commented Jan 30, 2020 at 3:45
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    Minor observation: the 6507 was designed for the Atari VCS, which has a reset button. On the original six-switcher it's labelled 'game reset' and positioned on the far right; by the 2600 Junior it's just 'reset' but still all the way on the right. That switch is the expected way to exit a game-in-progress, which otherwise would be a very tricky function to provide within the rest of the ROM/display bounds on that platform. So the answers below are right as to necessity in implementation terms, but on a 2600 that pin is also a necessity for the user interface.
    – Tommy
    Commented Jun 10, 2021 at 15:30
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    @Tommy: The reset button is merely an input to one of the RIOT's general-purpose I/O pins. If it were wired to the CPU reset function, the screen and audio would be frozen in some garbage state while it was held, and the television set would lose vertical sync. Although some games such as Tron Deadly Discs do a hard restart in response to the button, and lose vertical sync in the process, most games continue to run their normal frame loop while reset is held.
    – supercat
    Commented Jun 11, 2021 at 17:14

5 Answers 5


The hardware reset isn't an optional feature for a reset switch - it's an essential function for starting the CPU up correctly.

As the power supply rail rises, circuitry within the CPU, such as the register set, will take on random-ish values. The clock oscillator will unsteadily start working and CPU would start trying to operate before the supply was at a sufficient voltage for reliable operation and for interfacing with external circuitry.

When in reset, the CPU will load internal latches and certain registers in its register set with initial values. When the CPU is released from reset, it is ready to start executing cleanly as described in the datasheet.

So the circuit around the CPU must hold the CPU in reset until (a) the supply rails are within specification and (b) the oscillator has started up and steadied.

This is typically done by waiting a minimum time after power is applied before releasing reset. This is often 10 ms or longer. The power supply may be monitored until its reached the correct voltage then reset released a minimum time afterwards. The latter is more commonplace these days as all-in-one ICs for it have become cheap.


The 6502 data sheet (archived at http://archive.6502.org/) on page 2 gives the requirements for the RESET line as:

After Vcc reaches 4.75 volts in a power up routine, reset must be held low for at least two clock cycles. At this time the R/W and SYNC signals become valid.

As I recall from using the chip, a poorly designed POR (power on reset) circuit would often lead to intermittent failure to operate properly conditions.


Yes, you're correct.

The original 6500 family does not include a Power-On-Reset (POR) circuitry.

For reliable startup reset has to be pulled after power up. To avoid unintended execution of random code, it's recommended to keep Reset pulled by default and only release it after power is stabilized.

Then again, depending on your setup it may be acceptable not to do so. That's why one had to press Reset on the very first Apple II as well. On the Atari it was even more useful beyond startup, as reset is a great way to ... well ... reset any game, no matter what the internal state is. So without a Reset, some kind of interrupt would have been needed, eating up a pin anyway


Related to this - the Commodore VIC-20 uses a monostable 555 to hold the 6502 reset low for a few seconds after power on (the 555 output is inverted). The time is controlled by a 1µF capacitor - however if the capacitance has increased (it's been 40 years) then the reset will be held for longer: 2µF results in about a minute, which could lead one to think the machine was dead when really the reset line was simply being held low by the 555.


The reset pin on a processor serves two purposes:

  1. Ensure that the processor itself gets reset on power-up.

  2. Ensure that the processor does not try to fetch code from any external memory circuitry that isn't yet ready for use.

Given that the 6507 has a READY line, it might have been possible, and not even particularly difficult, to design the chip with an internal reset circuit that would go low when VDD goes to zero, and remain low unless or until the READY signal goes high. On the other hand, the amount of external circuitry required to ensure that READY would remain low until the power supply had stabilized, but still be functional for whatever other purposes it was needed, would be greater than the amount of circuitry that would be needed to generate a usable phi2 signal if that pin were omitted (pass a raw clock through an RC delay, and feed the CPU's phi0 with (original and not delayed), and the system's phi2 with (delayed and not original).

BTW, if the 6507 had phi1 and phi2 inputs, I suspect the Stella could have been designed to eliminate the need for READY by having a couple of WSYNC addresses, one of which would effectively slow the CPU clock to 1/12 speed except during the twelve cycles before horizontal blank, and one of which would stall the CPU during those ten cycles. So a store to WSYNC1 followed six cycles later by a store to WSYNC2 would align program execution with the beam without need for the READY line. Not sure if MOS's settlement with Motorola might have prevented them from selling a CPU with phi1 and phi2 inputs, however.

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