The reset pin on a processor serves two purposes:
Ensure that the processor itself gets reset on power-up.
Ensure that the processor does not try to fetch code from any external memory circuitry that isn't yet ready for use.
Given that the 6507 has a READY line, it might have been possible, and not even particularly difficult, to design the chip with an internal reset circuit that would go low when VDD goes to zero, and remain low unless or until the READY signal goes high. On the other hand, the amount of external circuitry required to ensure that READY would remain low until the power supply had stabilized, but still be functional for whatever other purposes it was needed, would be greater than the amount of circuitry that would be needed to generate a usable phi2 signal if that pin were omitted (pass a raw clock through an RC delay, and feed the CPU's phi0 with (original and not delayed), and the system's phi2 with (delayed and not original).
BTW, if the 6507 had phi1 and phi2 inputs, I suspect the Stella could have been designed to eliminate the need for READY by having a couple of WSYNC addresses, one of which would effectively slow the CPU clock to 1/12 speed except during the twelve cycles before horizontal blank, and one of which would stall the CPU during those ten cycles. So a store to WSYNC1 followed six cycles later by a store to WSYNC2 would align program execution with the beam without need for the READY line. Not sure if MOS's settlement with Motorola might have prevented them from selling a CPU with phi1 and phi2 inputs, however.