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The Cell, the CPU of the PlayStation 3, contained one conventional core called the PPE, and up to eight specialized vector cores called SPEs.

According to https://en.wikipedia.org/wiki/Cell_(microprocessor)

The PPE, which is capable of running a conventional operating system, has control over the SPEs and can start, stop, interrupt, and schedule processes running on the SPEs. To this end the PPE has additional instructions relating to control of the SPEs. Unlike SPEs, the PPE can read and write the main memory and the local memories of SPEs through the standard load/store instructions. Despite having Turing complete architectures, the SPEs are not fully autonomous and require the PPE to prime them before they can do any useful work.

Given that the SPEs have Turing complete architectures, what exactly stops them being fully autonomous? What feature do they lack, and what resource would it have consumed too much of on the chip, to design them with that feature?

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    I'm not familiar with the architecture, but this occurs to me on reading the above - where would an SPE be getting its program from? The SPE local program memory apparently needs to be loaded by the PPE, therefore the SPE is not autonomous. – another-dave Feb 1 '20 at 19:30
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    And as this is retrocomputing: You see this architecture in many old computers and supercomputers. There's a front end processor that bootstraps the system and controls and downloads code to a number of much more powerful main CPUs. The main CPUs could do this task, too, but it would just be a waste to use them for it. That's what you have the cheaper and simpler FPE for. – dirkt Feb 2 '20 at 4:43
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    Good point. Minicomputers too. The VAX 11/780, for example, had a PDP-11 console processor which initialized the VAX. – another-dave Feb 2 '20 at 14:55
  • @dirkt True, though in this case it is worth bearing in mind that the PPE was actually more expensive and complex than each SPE. – rwallace Feb 2 '20 at 15:19
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    is a question about the Playstation 3 on-topic here? I would think that the Ps3 would be too new – Matthew Barclay Feb 3 '20 at 0:57
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what exactly stops them being fully autonomous?

Nothing - except for the way any tight coupled multicore CPU starts up. After reset only the primary core starts executing code, while the rest is kept in a hold state, until prepared and released by the primary core. Further any control about the configuration can (usually) only be exerted by the primary core.

In case of the PS3 cores, this means only the PPE has the functionality to setup/start/stop a any SPE. So any OS must run on the PPE. Of course, it could as well run on the SPE, but the scheduler to assign tasks to cores has to run on the PPE. Eventually this includes many other central components/drivers, most notably memory and IPK drivers, as only the PPE can access all memory, while SPE are limited to their own. Not to mention generic I/O.

[In some way the setup is a distant remainder of classic Cray designs, were a general purpose I/O processor feeds specialized computing units - often itself supported by an external mainframe for schlepping the data - the I/O processor runs the OS, while the computing units do the 'superiour' work.]

In addition, the SPE are, as noted, reduced/specialized function version, so any code to run there must be made especially to fit this instruction set. Moving any task cross core only works between SPE, not between PPE and SPE or back (*1).

Due this limited nature assigning any task to a PPE has an overhead to be considered. Similar if this task requires intermediate I/O. They perform best if assigned long running self contained jobs.

A possible setup using the SPE as base for generic processing would effectively reduce the PPE to an I/O processor and making it a quite tight bottle neck.

Bottom line: Yes, in theory the SPE could be used for mundane tasks, but making them degrades the setup.


*1 - Yes, I'm aware, that come fine crafted code could be made to run on either, but beyond the most basic functions it will be a waste of resources one both.

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  • Actually, the Cray designs such as the CDC 6600 onward were the other way around; the single "main" processor was optimized for the arithemtical operations and did little else; there were multiple "peripheral processors" doing I/O, running the OS, and so on. – cjs Feb 19 '20 at 15:03
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What "prevents" it is the same thing that prevents graphics cards on modern PCs from running independently: there's simply no benefit to adding what would be needed to make them independent computers, and doing so what compromise the job that they're designed for.

The Cell Broadband Engine consists of one or more Power PC cores (Power Processor Elements or PPEs), which are fairly standard modern (for the time) CPU cores, along with a set of coprocessors (Synergistic Processing Elements or SPEs) optimized for mathematical tasks. You'll note the parallel here with the CPU+GPU combination found in modern gaming PCs. Whereas the PPEs are designed for general-purpose computing, the SPEs are designed for large, fairly repetitive numerical jobs where bandwidth and certain specific kinds of processing power are more useful than computational flexibility. The SPEs trade off general purpose flexibility and latency for better concurrency, bandwidth and raw numerical computational power.

Optimizing CPU hardware by splitting it into programmer-visible specialized units is not new. The CDC 6600 (the world's fastest computer from 1964 to 1969) used a similar technique but the other way around: the CP or Central Processor was optimized for arithmetic operations and there were ten (much slower and cheaper) PPs or Peripheral Processors that dealt with running the operating system, doing I/O and so on.

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    The random googling I did says that many graphics processors (which are surely the important part, not "cards") have conditional-branch instructions, which is the minimal requirement for control flow. – another-dave Feb 1 '20 at 19:40
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    @rwallace GPU's are Turing complete and have been for a long time. They are, like SPEs, very limited on what they can do practically. They read memory, perform some calculations and then write the results to memory. The CPU needs to direct this operation, telling the processing units what code to execute and what data process. At one point the SPEs may be doing physics calculations, at another they may be be performing vertex transformations on multiple independent models. There needs be some central authority directing all of this. – user722 Feb 1 '20 at 20:23
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    Even in SMP systems, there’s one CPU in charge of getting the full system up and running; the PPE/SPE split (and CPU/GPU, and big/little, and ...) is a special case of this. Given that a general-purpose CPU is used to assign tasks anyway, there’s no point in making specialised co-processors capable of doing so too. – Stephen Kitt Feb 1 '20 at 20:51
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    Calling the PPEs "fairly standard modern CPU cores" is a bit misleading, I think. While they implement the PowerPC ISA and are derived from the PPC970 (itself derived from the Power4), they are drastically simplified and e.g. don't support out-of-order execution (except for LOAD and STORE instructions). They were not designed to perform heavy computations, they were designed as orchestrators. I had a chance to talk to the lead designer of the AS/400, who were at the time also using a PPC970-derived CPU, and he hinted at the fact that the guys in Böblingen were running OS X on the PlayStation, – Jörg W Mittag Feb 1 '20 at 23:24
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    just for fun, but it was not a very pleasant experience. Implementing the PPC ISA and being able to sensibly run an unmodified PPC system are two different things. Linux also quickly supported the Cell BE, but it didn't really make sense to treat the PPE as a general-purpose CPU. Its purpose was to orchestrate the tasks delegated to the SPUs. The Xenon CPU used in the XBox 360 was based on three PPE cores, but again, the XBox 360 is not a general purpose computing system, and a lot of the heavy workload is offloaded to the GPU. – Jörg W Mittag Feb 1 '20 at 23:27

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