This is somewhat of a speculative question...

Amiga's 1985 Original Chip Set is inherently a 16bit architecture (the data bus is 16bit, registers are 16bit, the blitter itself is 16 state machines running in parallel, and sees the memory as 16bit words). This architecture could have been trivially extended to 32bit, which would have given twice the bandwidth without touching the overall design of a machine running synchronously to the video color clock.

The 32bit architecure arrived rather late in the form of the AA chipset (which also has a memory controller that do 2 cycles "fast page" RAM access, thus working, along with the 32 bit bus, at 4X of OCS's bandwidth).

Is there a technical reason I can't see of why Commodore did not go immediately for such a trivial improvement?

[I'm interested in technical reasons, rather than strategic (e.g. lack of retro-compatibility) or considerations on Commodore's "management". ]

  • 2
    Odd that my comment was removed. All I said was that there is nothing trivial about chip design. Even got a few up-votes. Why was my comment removed?
    – cbmeeks
    Jun 23, 2017 at 12:28
  • "This architecture could have been trivially extended to 32bit". I don't think that is the case. Even something as simple as the packaging might not be trivial to upgrade. You might have more pins than can be easily added to a DIP and thus have to repackage. That's before you even get into the actual chip design.
    – JeremyP
    Jun 23, 2017 at 13:07
  • I shouldn't have commented before reading the answers that both make the same point.
    – JeremyP
    Jun 23, 2017 at 13:09
  • 1
    @JeremyP don't worry...maybe your comment will be deleted like mine was.
    – cbmeeks
    Jun 23, 2017 at 13:30

2 Answers 2


One could just as easily ask why it was not extended to 64 bits, or even wider. Well, if you ignore backwards-compatibility and cost, yes, it could have been.

I'll pretend we can ignore backwards-compatibility and concentrate on cost first. Making the data pathways 32 bit would immediately double the number of transistors, with a corresponding doubling of the die size and cost to manufacture. However, it's worse than that, because the blitter contains a barrel-shifter (so that it can blit to pixel rather than word boundaries) which scales with the square of the number of bits, so that becomes four times bigger. There would also be the temptation to extend the video DAC from 4 bits per channel to 8, and the audio DAC from 8 bits to 16, which adds further cost. At least another 16 pins would also need to be added to the chip for the extra data lines.

In reality, increasing the die size and pin count makes the chip disproportionately more difficult and expensive to produce. The 68000 was a state of the art engineering marvel in that it was a huge DIP chip with 64 pins. Just reducing the pin count saved enough money that it was worth it for Motorola to make and sell the 68008 and other restricted-width chips.

Backwards-compatibility is however also important even though you dismiss it. The OCS chipset permits everything to be word-aligned, and so a replacement with a wider bus would have to handle misaligned accesses or stick to accessing in word-sized quantities. Intel x86 CPUs take the former approach, and pay for it in having a lot more transistors in its instruction decoder. AGA takes the latter approach and generally performs no better than OCS, except that there are some special high-bandwidth display modes that only work if the alignment is just right.

  • Thanks, really interesting answer. I'm not sure about the impact the barrel-shifter part on the overall costs, though, as the Blitter block diagram only show 2 32bit barrel shifter (which would have become 64bit) in the common part (i.e. not in the parts that are replicated 16 times - 32 times with my idea), which would have required "only" 2 x 224 more multiplexers according to Wikipedia.
    – user180940
    Aug 12, 2016 at 17:34
  • 1
    The Amiga was sufficiently bandwidth-constrained that even a modest improvement in throughput could have paid rather large dividends. Pushing the bus clock from 3.58MHz to 4.77MHz would have increased the bus bandwidth remaining in hires 16-color mode (which gobbles 1,920,000 words/second) from about 1660000 w/s to 2850000 w/s.
    – supercat
    Sep 20, 2016 at 22:48
  • 2
    The CDC6600 used a "shift columns" architecture, that essentially implemented shifting using a bunch of 2-1 multiplexers. The first column did a 1-bit shift, the second column did a 2-bit shift, the third did a 4-bit shift, and so on, by selecting which source bit fed the destination. Going from 32 to 64 bits in this requires doubling the width of the individual columns, and then adding one more column. (Analogous to radix-2 FFT butterfly layers.) Jun 22, 2017 at 19:28
  • 1
    Not only the 68008, but you had similar dynamics in other situations: the relationship between the 8086 and the 8088 was similar, with the 8086 sporting a 16-bit data bus and the 8088 having only an 8-bit data bus, but the two being otherwise very similar. Of course, even the 8086 only had 16-bit registers.
    – user
    Jun 22, 2017 at 19:31
  • @aCVn and pndc: My understanding was that the major savings with using an 8-bit external data bus on a 16-bit CPU (as with the 68008 and 8088) was actually in the rest of the system architecture: you could design for half the number of RAM chips, use cheaper 8-bit peripherals with less glue logic, save on design costs by reusing significant parts of existing 8-bit designs, etc.
    – cjs
    Oct 9, 2019 at 5:33

For the OCS, one big reason was chip package cost. Up to 40-pin DIP packages for the chips were the only ones in the consumer price range at the time the Amiga OCS was designed. Other chip packages with more pins (enough to allow a 32-bit bus) were several times more expensive, as they were meant for mainframes and aerospace applications.

For later designs, an alternative to doubling (or quadrupling) the number of transistors would have been to double the clock rate of the internal blit (etc.) logic, and multiplex one 32-bit memory bus cycle into two (or 4!) 16-bit internal graphic engine cycles. This would have been possible using the smaller, faster CMOS transistors available a few years after the OCS was designed. With a 2X internal clock multiple, the system could get twice the bandwidth from a 32-bit memory bus and similar speed DRAMs, but stay NTSC color burst synchronous.

  • I would think the biggest bang-for-buck win would have been to design the chipset so that instead of using independent 16-bit DRAM accesses for each and every video data fetch, each consisting of operations to set row, set column, access data, and delay for writeback, the video chip would access groups of four 16-bit words in the time that would otherwise be required to perform two independent 16-bit accesses. A normal DRAM access sequence can be split into three phases: row setup, column access, and writeback, but it's possible to access multiple columns within one sequence.
    – supercat
    Mar 5, 2022 at 21:20
  • Skipping the row-setup and writeback steps on three out of every four video fetches would effectively cut in half the amount of memory bandwidth used by video. In higher color modes, this change could more than double the amount of memory bandwidth available for other purposes, and thus allow all operations to be performed much faster, even if everything other than video was performed using the same means as it always had been.
    – supercat
    Mar 5, 2022 at 21:23

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.