Many 1-bit DRAM chips provide two pins for data communication, one for writing data (typically described as Din or D on datasheets) and one for reading data (Dout or Q). Examples I've found include the 2118, 4164, 41256, 4532, 4816, and 4116 (pictured below).

Pinout of TMS4116 DRAM

Computers such as the BBC Microcomputer, the Comomdore 64 (some revisions), and the ZX81's external 16K expansion used 1-bit DRAM chips with the data inputs and outputs wired together, and to a bidirectional data bus.

Wider (4-bit an 8-bit) DRAM chips didn't bother using separate input and output pins, possibly due to the larger number of pins that would have been required if they chose to do so.

Given that these machines made no use of the separate data inputs and outputs, I'm wondering why they were ever provided in the first place.

Can anyone explain how separate data inputs and outputs for RAM would be useful for a computer system designer?

Examples of machines that took advantage of this would be appreciated.

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    Two thoughts: (1) separate in/out makes for a nice buffer in some non-computer applications. (2) Separating in/out makes for easier circuitry if for only one bit, as noted going to four bits adds pinout problems. – Jon Custer Feb 5 '20 at 13:56
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    Complete speculation, but it almost looks like it's mimicking the interface to a D-type flip flop en.wikipedia.org/wiki/Flip-flop_%28electronics%29#D_flip-flop – Simon F Feb 5 '20 at 13:56
  1. Because there were spare pins otherwise.

  2. Because sometimes this could make the design simpler.

As an example, I'll put again schematics of a russian ZX clone, for example this one, named "Leningrad". All other clones with single DRAM set are made in a similar way.

Leningrad ZX clone schematics The inputs of DRAM chips (D21..28, labelled as 565RU5 -- russian analog of 4164) are connected directly to Z80 databus (D0..7). This means that CPU writes are processed directly to the DRAM, while at all other times (for example, ROM or IO access) DRAM chips won't disturb CPU bus and even could be read by video fetcher in parallel.

The outputs of DRAM chips are connected to the private bus (MD0..7), where the video data is taken from directly to the pixel shift register and attribute latches. The CPU reads are, however, passed through the D32 '373 latch, that temporarily connects both buses together.

If there were no separate input and output pins in the DRAM chips, the design would contain another latch for write data. Alternatively, where the explicit separation is not needed, having two pins does not hurt either.

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    A nice example, thanks. As an alternative to a second latch for write data, one could choose a bus transciever (e.g. 74ls245) instead. Or is there someting in the Z80's behaviour that needs latching, where a 6502-based machine doesn't? – Kaz Feb 5 '20 at 17:56
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    Probably the number of clock cycles Z80 takes to perform a write or read. 6502 always reads or writes inside a single clock. Z80 instead has two types of multiclock memory reads and a memory write cycle. Latches might help optimize memory-CPU interaction, for example when Z80 is reading, the memory makes single fast read cycle and then the latch "shows" info to the Z80 while its read sequence is in progress. – lvd Feb 5 '20 at 18:59

Can anyone explain how separate data inputs and outputs for RAM would be useful for a computer system designer?

There are several advantages:


  • Timing is only defined by address transfer
  • No additional requirement for access timing
  • Outputs is static, only defined by address input
  • No specific bus structure required
  • Any bus adaption (latches, buffers) is external

In addition it reduces the pincount quite a lot:

  • No direction signal needed
  • No output enable needed
  • No chip select needed (*1)

Thus even a 256 KiBit chip could be made into a 16 pin device (*2) keeping the pinout (mostly) compatible. It wasn't until the 1 MiBit that a new pinout was needed - which, as usual, did lead to some variation.

Bottom line: That way a RAM chip is just that, a RAM, without any additional circuitry.

Wider (4-bit an 8-bit) DRAM chips didn't bother using separate input and output pins, possibly due to the larger number of pins that would have been required if they chose to do so

Yes, as that would have pushed the pincount up to 22 for a 41464, which is rather unusual for 600 mil spacing, thus a switch to 600 mil would have had to follow, eating up much more board space, increasing cost further. Quite unhandy when considering that these x4 chips were mainly intended for cost reduced designs of conventional micros. Thus a reduction to only bidirectional bus designs was acceptable.

Examples of machines that took advantage of this would be appreciated.

There are not many with classic microprocessor designs, as they work with bidirectional busses anyway.

I once (~1983) did a video capture board using separate, not connected D/Q pins, working on a fixed (TV) timing frame(*3). Data input was continuous feed from an AD stage digitizing camera input and stored in RAM (/WR active). At the same time data output was feed synchronous feed into a DA stage creating output for a monitor (*4).

While WR was active, each frame was stored, overwriting the previous. By releasing WR (during retrace) the last picture stored was held, continued output displayed, and on demand transferred (*5) into the PC.

*1 - The original Mostek 4096 still required CS at pin 13.

*2 - Getting rid of additional voltages of the original 4116 freed pin 9 and 1 for A7 (4164) and A8 (41256)

*3 - Simply created by some counters triggered by filtered camera timing, so no internal clock source needed.

*4 - Well, since the system was meant to take employee photos, there were two screens, one 'regular' for the operator and a second with flipped Y axis to act like a mirror :)

*5 - Using a separate set of address counters and during retrace to not interference with the picture still displayed. It could have worked by reusing the picture counters, but that would have introduced a one frame flicker, which I did not want to happen, as it disturbs the UI process.

  • What is "direction signal"? "output enable" signal also might be useful for D-Q chips, but otherwise it is not obligatory since it could be emulated by asserting /CAS only on a specific chip that shares its Q bus or bidirectional bus with others. "Chip select" is also emulated by /RAS in the same manner. – lvd Feb 5 '20 at 19:06
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    @lvd Of course, as always, many more variations are possible, including a way to put dedicated signals into timing - like tall the way to serial addressing. But each will narrow down usability to more specific, less generic cases and requiring more external effort. The way it is is the most simple interface (except for address multiplexing) that can be used. – Raffzahn Feb 5 '20 at 19:16
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    "Bottom line: That way a RAM chip is just that, a RAM, without any additional circuitry." - Or in other words, separating the data input and output allows a system designer to isolate the RAM's outputs from the rest of the machine if they wish, but if they were tied together, the RAM chip would have to include Output Enable circuity to let them achieve the same goal? – Kaz Feb 6 '20 at 14:40

Although most often not used with microprocessor based systems, larger (mini, mainframe) systems often used unidirectional buses, which were easier to terminate to prevent reflections off of impedance mismatches. Long bidirectional buses might require termination at both ends, and heftier bidirectional line drivers to support the termination current. Separate input and output pins made connecting to unidirectional buses simpler.

(processor write-only) Video frame buffers are another example of something where unidirectional data buses might be used.


Example of a machine that tooke advantage of this

The Apple Macintosh IIfx used a special kind of memory modules with separated data input and output lines for all data bits. This allowed the designers to pipeline bus cycles (like continuing a write to RAM while already doing the next transaction on the bus or addressing the RAM while the previous transaction is still running) without the need to introduce dedicated tristate buffers for the RAM.

Example of another device that took advantage of this

I reverse engineered a 16-bit memory expansion card for the 80286 ISA bus. It had two banks of 18 chips each (16 data bits and two parity bits). The designers connected D and Q for the data bits only. They used separate D and Q for the parity chips. The input of the RAM is connected directly to the output of a 9-bit parity generator. The parity output of the RAM is connected via an AND gate to the 9th input pin of the 9-bit parity generator. During write cycles, the parity output is masked via that and gate, and the required parity bit is presented to the D pin of the RAM. During read cycles, the AND gate passes the actual parity bit to the parity generator (now used as verifier) and the ouput of the parity generator is used to drive the NMI line to indicate a parity error.

This design was likely common in PC-type computers, as the 30-pin SIMM standard follows this pattern: combined DQ pins for the data bus, but separate D and Q pins for the parity bit.

Anecdotal side story

I own 4 30-pin SIMMs that are of sub-standard quality and short Parity D to Parity Q internally on the module. They contain three 4Mx4 chips for a 4Mx12 array and 0-ohm solder links to pick any 3 bits from each of the chips to provide a 4Mx9 interface to the computer. I used them in a 486 computer for a short time, where there were no issues with the parity bit (no surprise, as parity bits are part of the 486 front-side bus, so putting these bits on the bidirectional bus makes absolute sense).

I found out about the non-conforming module only after taking a deeper look into them because they corruptes data bits during normal operation. I am quite confident that the 4Mx4 chips on that module are relabeled factory rejects.

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