# In the Amstrad CPC's Mode 0, what was the design rationale for interleaving the pixel bits?

The following tables are modified and corrected from Painting pixels: Introduction to video memory.

### Mode 2 - 640x200 (half width pixels), 2 colours

memory bit 7 6 5 4 3 2 1 0
pixel 0 1 2 3 4 5 6 7
pixel bit 0 0 0 0 0 0 0 0

### Mode 1 - 320x200 (single width pixels), 4 colours

memory bit 7 6 5 4 3 2 1 0
pixel 0 1 2 3 0 1 2 3
pixel bit 0 0 0 0 1 1 1 1

### Mode 0 - 160x200 (double width pixels), 16 colours

memory bit 7 6 5 4 3 2 1 0
pixel 0 1 0 1 0 1 0 1
pixel bit 0 0 2 2 1 1 3 3

The arrangement of pixels makes sense for each mode. One ascending group of eight pixels, two ascending groups of four pixels, four ascending groups of two pixels.

The bit patterns per pixel make sense for modes 2 (all `0`) & 1 (four `0`s, then four `1`s), although it might have made more sense to have the high bits first. However, for mode 0 it goes `0`, `2`, `1`, `3` (`2` & `1` are swapped compared to ascending order). Why not use simple ascending order? I assume there was some advantage to aligning memory bits `3` & `2` (and also `7` & `6`) to their pixel bits between modes 1 and 0.

• Making the p-bits run in numerical sequence would require that p-bit 1 of pixel 0 come from a different place in modes 0 and 1. Commented Feb 7, 2020 at 23:23
• @supercat Yes, I mentioned that in the question. Commented Feb 7, 2020 at 23:25
• Making p-bit 1 of pixel 0 come from a different place in modes 0 and 1 would require routing circuitry which can be omitted if the bits are arranged as you show them. Commented Feb 7, 2020 at 23:30
• I haven't looked at the Amstrad schematic, but a typical design would load each memory byte into a shift register and then shift the bits at the pixel rate. For mode 2, just use bit 7 and shift at full speed. For mode 1, use bits 7 and 3 and shift at half speed. For mode 0, use bits 7, 3, 5, and 1, and shift at 1/4 speed. Using the "weird" order makes it possible for color bit to use the same bit 3 tap as in mode 1. Commented Feb 7, 2020 at 23:43
• @supercat An answer that addresses this from a hardware perspective of the 6845 CRTC would be good. Commented Feb 8, 2020 at 1:09

According to the CPC schematic, the Armstrad uses a gate array to generate video, so we'd need to know how this gate array is programmed for an exact explanation.

But expanding on the comment of supercat, we can do an educated guess:

Assume we have an 8 bit shift register in the gate array, with a tap for bit C0 at the end, a tap for bit C1 in the middle, a tap for bit C2 two bits from the end and a tap for bit C3 two bits from the other end. These 4 bits C0..C3 go to the color generation part. Picture:

``````D0 ---> D1 -+-> D2 ---> D3 -+-> D4 ---> D5 -+-> D6 ---> D7 --+
|               |               |                |
V               V               V                V
C3              C1              C2               C0
``````

Then for Mode 2, we can clamp all bits except bit 0 to zero, for two colors in the format given above.

For Mode 1, we only clamp bits C3 and C2 to zero, leaving bit C0 and bit C1 for four colors in the format given above.

And finally for Mode 0, there is no clamping, leaving all four bits for 16 colors in the format given above.

If you wanted a more "logical" format for Mode 0 instead, you'd need extra logic to swap around the four bits from the way they can also be used in Mode 1 and Mode 2 to the way you want for Mode 0. The gate array doesn't contain this extra logic, because it would use up gates that can be used for other purposes, and therefore you end up with the "weird" ordering.

• I don't see how that would help, in mode 0 you would need logic gates to push the shift register for 4 clocks between every sample. In mode 1 it would be 2 clocks. The circuitry needed to manage those would most likely offset those gains or at least be close enough that it would not matter that much. Commented Mar 4, 2023 at 6:02
• @LaurentGiroud picking a clock source from an existing clock divider (which you probably need anyhow for other purposes) is extremely cheap. Commented Mar 4, 2023 at 10:28
• True, using the hires clock would be enough. This said, any logic that is used to clamp the C3/C2 bits for mode 2, C1 for mode 1 would be equally functional with consecutive bits since in all cases the most significant bits are the only ones that need sampling and they will be arriving first in the shift register. The two solutions would essentially require the same number of gates. Commented Mar 6, 2023 at 0:49

I am not an expert in Amstrad CPC at all, however I can see some regularities, for example:

1. Not grouping pixel bits in halves (like pixel 0 takes bits 7..4 and pixel 1 takes bits 3..0) allows one to use single shift register, that always shifts by 1 bit. In mode 2, it shifts 8 times for 8 pixels, in mode 1 it shifts 4 times for 4 pixels, where one pixel is always taken from bits 7 and 3, second one from bits 6 and 2, etc. Same with mode 0, where every of two pixels takes its bits from 4 positions in the shift register.

2. A funny bit layout in mode 0 also has its logic, because, in comparison with mode 1, half of bits for a pixel are taken from the same positions. For "0-0-1-1-2-2-3-3" layout, there would be only single such position.