Why AND instruction updates flags in the fetch step?
Others logic instructions like ORA and EOR update flags in the same step that they update accumulator, in the decode step.
Is it a bug of visual6502? Is it a bug of 6502? Is it the normal behaviour?
cycle ab db rw Fetch pc a x y s p
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0 0000 29 1 AND # 0000 aa 00 00 fd nv‑BdIZc ; AND #$FE
0 0000 29 1 AND # 0000 aa 00 00 fd nv‑BdIZc
1 0001 f0 1 0001 aa 00 00 fd nv‑BdIZc
1 0001 f0 1 0001 aa 00 00 fd nv‑BdIZc
2 0002 ea 1 NOP 0002 aa 00 00 fd Nv‑BdIzc ; Fetch opcode, Update flags here
2 0002 ea 1 NOP 0002 aa 00 00 fd Nv‑BdIzc
3 0003 ea 1 0003 a0 00 00 fd Nv‑BdIzc ; Decode opcode, Update accumulator here
3 0003 ea 1 0003 a0 00 00 fd Nv‑BdIzc
cycle ab db rw Fetch pc a x y s p
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0 0000 49 1 EOR # 0000 aa 00 00 fd nv‑BdIZc ; EOR #$FF
0 0000 49 1 EOR # 0000 aa 00 00 fd nv‑BdIZc
1 0001 ff 1 0001 aa 00 00 fd nv‑BdIZc
1 0001 ff 1 0001 aa 00 00 fd nv‑BdIZc
2 0002 ea 1 NOP 0002 aa 00 00 fd nv‑BdIZc ; Fetch opcode
2 0002 ea 1 NOP 0002 aa 00 00 fd nv‑BdIZc
3 0003 ea 1 0003 55 00 00 fd nv‑BdIzc ; Decode opcode, Update accumulator and flags here
3 0003 ea 1 0003 55 00 00 fd nv‑BdIzc
cycle ab db rw Fetch pc a x y s p
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0 0000 09 1 ORA # 0000 aa 00 00 fd nv‑BdIZc ; ORA #$FF
0 0000 09 1 ORA # 0000 aa 00 00 fd nv‑BdIZc
1 0001 ff 1 0001 aa 00 00 fd nv‑BdIZc
1 0001 ff 1 0001 aa 00 00 fd nv‑BdIZc
2 0002 ea 1 NOP 0002 aa 00 00 fd nv‑BdIZc ; Fetch opcode
2 0002 ea 1 NOP 0002 aa 00 00 fd nv‑BdIZc
3 0003 ea 1 0003 ff 00 00 fd Nv‑BdIzc ; Decode opcode, Update accumulator and flags here
3 0003 ea 1 0003 ff 00 00 fd Nv‑BdIzc