I am writing a basic Zilog Z80 assembly language interpreter and something I noticed as I went through the 8 bit load commands is that the estimated times for LD (IX+d), n and LD (IY+d), n are different (4.75 and 2.50 respectively. Is this a typo as I suspect or is there a valid timing difference between these otherwise fairly identical operations?

  • Must be equal. Where have you found these numbers, is there a link?
    – tum_
    Feb 11, 2020 at 10:17
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    Why are you dealing with times instead of T states in a Z80 interpreter? And thats a good point, where are you seeing those times? They can be taking into account external factors like memory/Z80 contention. Feb 11, 2020 at 10:19
  • I'm not really dealing with times although I might record them for interest sake, I was more interested in whether there was a mistake or not. Link to manual is zilog.com/…
    – mwarren
    Feb 11, 2020 at 10:32
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    @mwarren It is obviously a bug in documentation. Those two pages were certainly edited based in the HL instruction, and someone forgot to edit that value to reflect the IY timing. Feb 11, 2020 at 10:45
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    @mwarren also take a look at What are tacts in the context of ZX Spectrum systems? as to why is better to use [T] instead of [sec] for runtime of code measuring
    – Spektre
    Feb 11, 2020 at 12:53

2 Answers 2


Those two mnemonics opcodes are known to have the same timing / same inner mechanisms of mapping into HL.

It is obviously a bug in documentation from the link you give us. Those two pages you mention (86 and 87) were certainly edited based in the HL instruction, and someone forgot to edit that value to reflect the IY timing.

Also, do not focus much in single details. If they have the same T times described, they shant have different execution times in the theoretical times in the datasheet.

  • >they shant have different execution times. - In theory, IX and IY can point to memory with different performance but that's a different story completely...
    – tum_
    Feb 11, 2020 at 11:33
  • @tum_ Indeed, I commented contention in the question. Clarified nonetheless. Feb 11, 2020 at 13:30
opc      T0 T1 MC1   MC2   MC3   MC4   MC5   MC6   MC7   mnemonic
DD36S1U2 23 00 M1R 4 M1R 4 MRD 3 NON 5 MRD 4 MWR 3 ... 0 LD (IX+S8),U8
FD36S1U2 23 00 M1R 4 M1R 4 MRD 3 NON 5 MRD 4 MWR 3 ... 0 LD (IY+S8),U8

As you can see, the timings (T0/T1) are identical. Beware most Z80 instruction set docs contain errors (even those which claim to be 100% correct).

While I developed my ZX emulator, I compiled a lot of isets and by painful comparison (in MySQL) and inference, I created my own Z80 iset table which can be found in What's the proper implementation for hardware emulation?, containing the secret instructions and inferred machine cycle timings etc. and passing ZEXALL 100%. I think you might find it useful for your task ...

  • Thank you for that info, it will be most useful. Sorry I can't tick your answer as well but I upvoted.
    – mwarren
    Feb 11, 2020 at 11:20
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    @mwarren no problem the first answer is valid and where here first ...
    – Spektre
    Feb 11, 2020 at 11:22
  • Hmm, 23 T States for LD (IX+d),n does not seem correct to me. All the specifications I've seen and used give 19 (4,4,3,5,3) (as in the OP's link). 23 T is for INC (IX+d), RLC (IX+d), etc. where you have both data memory read and write. Are you sure your numbers are correct?
    – tum_
    Feb 11, 2020 at 21:31
  • On a second thought, you're probably right. The Zilog specs give the same 19 T States for LD (IX+d),n and for LD (IX+d),r which can hardly be correct. It should take an extra read to fetch the immediate, so +4 is logical. You live and you learn...
    – tum_
    Feb 11, 2020 at 21:45
  • @tum_ there where a lot of discrepancies among all docs I inspected at that time but once I stumped on some MC level timings form Zilog (even it was also wrong) I changed the timings to MC cycles and suddenly it started make sense even for the crazy 4 Byte instructions... And ZEXALL showed me which instructions where done correctly (IIRC it uses r register for checksum so its timing dependent too) so I fit all the instructions and as the machine cycles are usually the same I was able to correct my iset pretty fast
    – Spektre
    Feb 11, 2020 at 21:59

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