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Does anyone have a quick primer to the way the 6800's compare-and-branch instructions worked internally? I'm referring to the instructions like BLS that compared a value in memory to the accumulator.
I guess that it automated the process of doing an internal LDA,SBC,BNE sort of thing, but that would seem to require an additional internal register for holding the value during comparison?
Like many other machines, the 6800 has a compare instruction CMP that compares the accumulator with another operand, specified just as it is in other instructions like ADD and SUB. The CMP instruction, like ADD and SUB, sets the four condition code bits NZVC according to the arithmetic result -- in fact, it is identical with a SUB instruction, except that the result is not written back to the accumulator.
A subsequent conditional branch instruction such as BLS examines the condition code and branches if the condition is satisifed. In the case of BLS, the branch happens if either the C bit of the Z bit is set (or both).
Note that many other instructions set the condition code -- too many to list here. It's common for the instruction immediately preceding the BLS to establish the condition code that is used to decide whether to branch. That instruction doesn't have to be a CMP: it could be an ADD or SUB, or some other instruction entirely. In more tricky code, an earlier instruction might generate the condition code, provided intervening instructions do not modify the relevant bits. Understanding such code entails knowing which instructions set which condition bits, something that distinguishes hot-shot coders from mere mortals like me. My head is not big enough to memorise the details for more than one machine architecture.
[Edit] Source: The M6800 Programming Reference Manual on my desk.
I guess that it automated the process of doing an internal LDA,SBC,BNE sort of thing, but that would seem to require an additional internal register for holding the value during comparison?
A common way to implement this kind of operation (used on 6502, Z80, at least the early PDP-11s), is to have the ALU compute the subtraction, and then discard the result.
Let's take the 6502 as an example. The ALU unconditionally puts its result onto an internal bus, and then the value on the bus may be latched into any of the registers. So, by not latching the result into a register, the cmp instruction comes almost for free if you have a subtract operand. The Z80 works in a similar way, and I bet the 6800 does too.
You can find out exactly how it works over at Visual6502. Their 6800 simulation appears http://www.visual6502.org/JSSim/expert-6800.html
CMP.