This question triggered a brain cell.

I remember a computer architecture, possibly one that was known for its beautifully symmetric instruction set, with an assortment of distinct mnemonics for different conditional branch instructions. All were of the form JUMPxx where the xx named the condition. I don't remember the exact spelling of any but two of them

  • JUMPA meant "jump always," and
  • Just plain JUMP meant "jump never" (i.e., the assembler allowed you to write "JUMP effective address," but it silently ignored the address expression, and it emitted a no-op.)

What architecture am I remembering?

  • 3
    Minor notes. The conventional PDP-10 mnemonic is JUMP, not JMP. The assembler doesn't ignore the address expression; it's put into the instruction. It's also not entirely ignored by the processor since all instructions start with an effective address computation. Commented Feb 27, 2020 at 12:45
  • 6
    Sounds stupid. Pity the person reading that code.
    – Caltor
    Commented Feb 27, 2020 at 12:46
  • 5
    Not at all -- it was gloriously systematic (whole instruction set , not just jumps) and therefore easy to read. Even for a callow undergrad such as myself. In terms of documentation, I think all JUMPxx were documented on one page, and therefore it was perfectly obvious that the 'xx' suffix described the jump conditions.
    – dave
    Commented Feb 27, 2020 at 14:39
  • 4
    @Caltor - one more thing: someone merely reading code is unlikely to see a plain JUMP to be confused by, since AFAIK there is in general little reason to write it. It's a known no-op; if you want a no-op there are more conventional choices. In general, a highly regular instruction set will have several operations that are effectively no-ops.
    – dave
    Commented Feb 27, 2020 at 22:02
  • 1
    You can't "leave out" the opcode from the hardware, it's the natural result of the regular way that the instruction is coded. And since there's an opcode, it surely deserves an assembler mnemonic. I'm not sure what distinguishes a genuine no-op from any other no-op, though.
    – dave
    Commented Feb 28, 2020 at 13:59

2 Answers 2



It had a very orthogonal instruction set based around mnemonics with suffixes, and depending on the operation, sometimes no suffix meant a NOP.


  • I emphased the important part a bit, as could be almost missed. Still, it would great if you could make it more wasy to read - and turn the link as well into an informative sentence about what it is about/what is shown when followed.
    – Raffzahn
    Commented Feb 26, 2020 at 18:20
  • 13
    And of course if you want to jump always, you don't actually use JUMPA, you use JRST, which is "jump and restore nothing" (the AC field in a JRST qualifies what the instruction actually does).
    – dave
    Commented Feb 26, 2020 at 19:12
  • 2
    And, for completeness: SKIPx worked the same way. In particular, SKIP doesn't skip. There were also oddities like SETMM, which reads a word out of memory and writes the same value to the same location, IOW a no-op which writes memory. This sort of thing led to interesting discussions such as "what is the fastest no-op on model X?"
    – Mark Wood
    Commented Feb 28, 2020 at 4:13

Although this isn't the processor you're thinking of, another example is that of early ARM chips, which allowed all instructions to have a condition field, the default being AL (always), and also included NV (never).

The NV condition was however deprecated/removed in later chips.

See for example: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0027d/DDI0027D_7di_ds.pdf page 26

If the always (AL) condition is specified, the instruction will be executed irrespective of the flags. The never (NV) class of condition codes shall not be used as they will be redefined in future variants of the ARM architecture. If a NOP is required it is suggested that MOV R0,R0 be used. The assembler treats the absence of a condition code as though always had been specified.

The use of conditions on any instruction was very useful to avoid short branches that would flush the pipeline.

So for example (remembering back at least two decades):

x = x - 100;

if (x < 0)
  x = 0;

...could become:

SUBS  R0, R0, #100 // Subtract literal 100 from R0, store in R0, and set flags.
MOVLT R0, #0       // Assign zero to R0 ONLY IF the arithmetic flags indicated less-than zero.

...instead of using (say) a BGE to skip over the assignment.

  • 3
    On modern ARM in the standard ARM32 operation mode, it is still the case that all normal instructions can be conditionally executed. As far as I'm concerned, only floating point and vector instructions cannot as they have been stuffed into the encoding space of what would otherwise be NV-predicated instructions.
    – fuz
    Commented Feb 27, 2020 at 23:36
  • 2
    The default condition for all instructions is AL (except maybe NOP if that's encoded with an NV predicate). So for example b = bal. (Which can be confusing to people used to MIPS or other RISC ISAs, where MIPS jal / bal is jump/branch-and-link; the ARM equivalent is bl branch-and-link to save a return address. ARM bal is just Branch ALways, not saving a return address in the link register.) Commented Feb 28, 2020 at 1:10

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