TL; DR: Because it is not a 16-bit device, as it has a multiplexed 8-bit address/data bus, and giving 64 IO addresses from the 256 reserved to PC motherboard devices would have been too much, so access to it was split into two IO ports, one to send address and another to read/write data.
As the chip does not have a separate address and data buses, they are multiplexed into one 8-bit address/data bus, to save IO pins. So basically the bus has two phases for each read or write; first the address write phase, and then the data read/write phase.
As it was a Motorola real-time clock chip, it could be directly connected to a compatible Motorola CPU with multiplexed address/data bus as memory-mapped IO, so it can be simply used like memory chip, reading and writing 8-bit data to one of the 64 registers at some base address.
But when it was used on IBM AT motherboard that has a 16-bit 80286 CPU, and all the motherboard IO devices already needed to be on a non-multiplexed IO bus for backwards compatibility with PC and TX, first some complex logic interfacing was needed to connect it like the other IO peripherals with non-multiplexed bus. It would have also been too much to give it 64 directly mapped IO addresses, as all the motherboard devices were reserved to be on the first 256 addresses. Therefore two IO ports were allocated, 0x70 to send the address cycle, and 0x71 to send the register data cycle.
It was also considered a slow device, so many BIOSes had delays between address and data cycles.
And on the IBM AT, there was no mechanism to convert 16-bit IO cycles to two 8-bit IO cycles for the even motherboard addresses, only a mechanism to forward 8-bit access cycles on the high 8-bit bus to low 8-bit bus so 8-bit bus is enough for odd and even addresses.
Later clone computers with different chipsets and BIOSes were of course free to change all what IBM first did, allowing the CPU to use 16-bit IO to write RTC address and data in one cycle. Integrating or cloning the RTC functionality into the chipset as well also removes the limitation of accessing a real RTC chip via multiplexed 8-bit bus.