Why can’t the RTC (0x70, 0x71) read and write 16 bits at a time? For example:

        mov     ax, 0xa8f
        out     0x70, ax

I have found in a 286 BIOS that did this (BIOS ID string: S286-6181-101590-K0):

00005357  B87253            mov ax,0x5372
0000535A  26A36704          mov [es:0x467],ax
0000535E  B800F0            mov ax,0xf000
00005361  26A36904          mov [es:0x469],ax
00005365  B88F0A            mov ax,0xa8f
00005368  E770              out 0x70,ax
0000536A  E814C1            call word 0x1481
0000536D  B0FE              mov al,0xfe
0000536F  E664              out 0x64,al
00005371  F4                hlt

2 Answers 2


TL; DR: Because it is not a 16-bit device, as it has a multiplexed 8-bit address/data bus, and giving 64 IO addresses from the 256 reserved to PC motherboard devices would have been too much, so access to it was split into two IO ports, one to send address and another to read/write data.

As the chip does not have a separate address and data buses, they are multiplexed into one 8-bit address/data bus, to save IO pins. So basically the bus has two phases for each read or write; first the address write phase, and then the data read/write phase.

As it was a Motorola real-time clock chip, it could be directly connected to a compatible Motorola CPU with multiplexed address/data bus as memory-mapped IO, so it can be simply used like memory chip, reading and writing 8-bit data to one of the 64 registers at some base address.

But when it was used on IBM AT motherboard that has a 16-bit 80286 CPU, and all the motherboard IO devices already needed to be on a non-multiplexed IO bus for backwards compatibility with PC and TX, first some complex logic interfacing was needed to connect it like the other IO peripherals with non-multiplexed bus. It would have also been too much to give it 64 directly mapped IO addresses, as all the motherboard devices were reserved to be on the first 256 addresses. Therefore two IO ports were allocated, 0x70 to send the address cycle, and 0x71 to send the register data cycle.

It was also considered a slow device, so many BIOSes had delays between address and data cycles.

And on the IBM AT, there was no mechanism to convert 16-bit IO cycles to two 8-bit IO cycles for the even motherboard addresses, only a mechanism to forward 8-bit access cycles on the high 8-bit bus to low 8-bit bus so 8-bit bus is enough for odd and even addresses.

Later clone computers with different chipsets and BIOSes were of course free to change all what IBM first did, allowing the CPU to use 16-bit IO to write RTC address and data in one cycle. Integrating or cloning the RTC functionality into the chipset as well also removes the limitation of accessing a real RTC chip via multiplexed 8-bit bus.

  • It's too bad that IBM didn't decode more I/O address bits, since I/O address space could otherwise be plentiful. Add a 74LS138, drive its enable with A15 and its select inputs with A14-A12, send output 0 to the motherboard I/O devices, and one of the remaining outputs to each card slot, and the motherboard and each I/O cards could get have 4K of I/O address space all to itself. If it's necessary to go beyond seven cards, add another 74LS138 to get another eight.
    – supercat
    Oct 7, 2020 at 22:49
  • @supercat The cards are free to decode the address bus themselves, so it is not that bad. For every 10-bit base address, the card may ignore the 6 other bits or use them for futher decoding. For example Sound Blaster can have the base at 220h and it can use 620h for the wavetable extensions. Multi port UART cards also use the high 6 address bits to select which UART chip is selected.
    – Justme
    Oct 8, 2020 at 4:58
  • It is possible for cards to decode things in that fashion, but it will still be necessary to add jumpers to configure what address each card should use. If the motherboard had included a 74LS138 that would assign each card a 4K region of address space, cards could have added automatic plug-and-play support using a 74LS373 or equivalent wired to output onto the data bus, with each of its D0-D7 wired to one of the address pins A0-A7, making giving 24 bits worth of identification/configuration data available to the BIOS.
    – supercat
    Oct 8, 2020 at 20:02

Edit: Made a mistake, JustMe has the correct answer. I was thinking the XT had an RTC, but it was an AT specific thing so the rationale for the 8 bit writes is chipset related and not directly on the 8086 bus.

Old post below.

TL;DR: Because the CMOS chip might only have an 8 bit data interface.

Full Detail:

An 8 bit I/O operation and a 16 bit I/O operation are fundamentally different things on an x86 CPU. At a logical level (because modern iterations of the processor are pretty far removed from the signalling of the 8088/8086), they behave as follows:

8 Bit OUT:

  • Indicate 8 bit operation
  • Latch Address lines to address specified
  • Latch Data in the lower 8 bits of the Data lines

16 Bit OUT to even location on an 8086:

  • Indicate 16 bit operation
  • Latch Address lines to address specified
  • Latch Data in the 16 bits of the Data lines

16 Bit OUT to odd location, or any 16 Bit OUT on an 8088:

  • Indicate 8 bit operation
  • Latch Address lines to address specified
  • Latch low 8 bits of Data in the 8 bits of the Data lines


  • Indicate 8 bit operation
  • Latch Address lines to address specified + 1
  • Latch high 8 bits of Data in the 8 bits of the Data lines

(Source: 8088/8086 Hardware Reference Manual - best to read it for exact details on how A0 and /BHE work together on the 8086)

Now, in the case of CMOS, the MC146818 and other similar chips that implemented the port 0x70/0x71 interface had an 8 bit interface. This meant that for an 8086 to talk to in properly it needed to use the 8 bit version of the operation or the CMOS itself would never see the top 8 bits of the write, given they were directly connected to the ISA bus with various logic gates to control the activation of the chip on only the 0x70/0x71 addresses.

These days with the entire CMOS, and most other old-school backward compatible stuff being implemented entirely in the chipset it likely doesn't matter - depending on exactly how diligent they were in their compatibility efforts (a PCI device is entirely at liberty to respond differently to a 16 bit transaction at an address than it does two 8 bit transactions at consecutive addresses, for example). If you're writing a BIOS for a specific chipset then you know exactly how it behaves so you can use whatever is appropriate, but if you're writing a general purpose app/OS then you have to implement what is guaranteed to work - the separate byte level OUT statements.

  • The RTC does have 8-bit interface, it fact a multiplexed address/data bus, so it has more complex logic interfacing it to CPU. The 16-bit CPU only will convert 16-bit operation to odd address to two IO 8-bit operations; first on high 8-bit data bus only and the second on low 8-bit data bus. The CPU does not know if you have a 8-bit or 16-bit device on even address, so it is the job of the chipset to perform the conversion to two consecutive 8-bit addresses at low 8-bit bus. And the IBM AT chipset does not do this for motherboard IO addresses. It just routes odd 8-bit accesses to low 8-bit bus.
    – Justme
    Feb 28, 2020 at 12:04
  • Thanks. Got confused with the multiplexed 8088/8086 bus compared to the 80286 (and ISA) having the discrete signalling.
    – throx
    Feb 28, 2020 at 23:20

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