The Intel 8253/8254 timer, in its default configuration, triggers IRQ0 18.2 times per second. Why this strange rate, and not something like 60 Hz (to match the most common video refresh rate) or 100 Hz (to give a round number)?


The first CGA PCs used a single clock from which they derived all their timings. To allow for NTSC output, the main clock had to run at a multiple of the colour subcarrier frequency; the main clock ended up running at 14.31818 MHz, i.e. four times the NTSC colour subcarrier frequency. (This explains the 4.77 MHz frequency of the first PC: that's 14.31818 ÷ 3. IIRC these values were chosen as the best compromise between NTSC compatibility and the sustainable clock-rates with the first production 8088 chips...)

This clock feeds the 8254, whose channel 0 ticks at 1.193 MHz (one twelfth of the main clock rate); a programmable counter is decremented every time this happens, and when it rolls over, IRQ0 fires. The standard PC setup uses the highest possible rollover value, 65536, resulting in the slowest possible IRQ0 firing rate; 1.193 ÷ 65536 is 18.2 Hz.

This page has lots of detail on the 8253 and 8254. Wikipedia covers the frequency selection to some extent. I think some of the blog posts on the 8088 MPH demo covered this too, but I haven't found the ones I'm thinking of just now.

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    I wonder why they didn't use 65,544 as a divisor, which would have resulted in there being 65536.434 ticks per hour, so each tick would have been 3600/65536.434 of a second--a value that could be easily worked with using 16x16->32 multiplication. – supercat Sep 2 '16 at 17:01
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    @supercat which divisor are you referring to? The divisor applied to channel 0? It's a 16-bit counter, so the maximum possible value is 65536. – Stephen Kitt Sep 2 '16 at 17:23
  • For some reason I slipped up as to which side of 65536 the figure was. Mea culpa. I do find it interesting that the rate they picked works out so close to 65,536 ticks/hour. – supercat Sep 2 '16 at 19:15
  • Speculation, but I wonder if they did not select a higher rate in order to keep the impact of all those interrupts on performance minimized? – Brian Knoblauch Sep 19 '18 at 16:56

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