# Why is the 8254's default rate 18.2 Hz?

The Intel 8253/8254 timer, in its default configuration, triggers IRQ0 18.2 times per second. Why this strange rate, and not something like 60 Hz (to match the most common video refresh rate) or 100 Hz (to give a round number)?

• Note that a 60 or 50 cycle clock (depending on country) can and has often been implemented with a simple circuit converting the AC line in sine wave to attenuated pulses. Commented May 15, 2020 at 16:53

The first CGA PCs used a single clock from which they derived all their timings. To allow for NTSC output, the main clock had to run at a multiple of the colour subcarrier frequency; the main clock ended up running at 14.31818 MHz, i.e. four times the NTSC colour subcarrier frequency.

This clock feeds the 8254, whose channel 0 ticks at 1.193 MHz (one twelfth of the main clock rate); a programmable counter is decremented every time this happens, and when it rolls over, IRQ0 fires. The standard PC setup uses the highest possible rollover value, 65536, resulting in the slowest possible IRQ0 firing rate; 1.193 ÷ 65536 is 18.2 Hz.

This page has lots of detail on the 8253 and 8254. Wikipedia covers the frequency selection to some extent. I think some of the blog posts on the 8088 MPH demo covered this too, but I haven't found the ones I'm thinking of just now.

This explains the 4.77 MHz frequency of the first PC: that's 14.31818 ÷ 3. This value was chosen to save a little money: the 8088 has a 1/3 duty cycle, so the 8284 clock generator runs at three times the speed of the 8088, and using a 14.31818 provided the correct NTSC clock with a 1/4 divisor, and a clock close to the rates speed of 15MHz for the 8284 and 5MHz for the 8088. See Tim Paterson’s article on the topic for details.

• I wonder why they didn't use 65,544 as a divisor, which would have resulted in there being 65536.434 ticks per hour, so each tick would have been 3600/65536.434 of a second--a value that could be easily worked with using 16x16->32 multiplication. Commented Sep 2, 2016 at 17:01
• @supercat which divisor are you referring to? The divisor applied to channel 0? It's a 16-bit counter, so the maximum possible value is 65536. Commented Sep 2, 2016 at 17:23
• For some reason I slipped up as to which side of 65536 the figure was. Mea culpa. I do find it interesting that the rate they picked works out so close to 65,536 ticks/hour. Commented Sep 2, 2016 at 19:15
• Speculation, but I wonder if they did not select a higher rate in order to keep the impact of all those interrupts on performance minimized? Commented Sep 19, 2018 at 16:56
• @BrianKnoblauch If memory serves, that was the reason. On a single-user machine there is no need to have an interrupt rate higher than "the blink of an eye" for whatever background functions there might be, and there is not much point making it a nice-looking fraction like 1/20. Commented May 15, 2020 at 18:23