As with most NMOS processors, the NMOS versions of the 6502 (and even earlier CMOS versions) do not have a static core. Thus, if you run the clock too slowly or stop the clock for too long while doing clock stretching, internal latches will lose their data and the 6502 won't work properly.
For how long could you stop the clock on a 6502 without running into problems?
Official figures vary, and are sometimes wrong. Evidence indicates that not exceeding to 5-6 microseconds is fine.
In Jim Sather's book Understanding the Apple II he has a rough transcript of an interview with Steve Wozniak. On page I-3 they discuss this exact issue.
W. I'll tell you about a timing problem that will interest you. My first design for the Apple II used a display method in which the 6502 was stopped for 40 microseconds. The Synertek data sheet said you could stop it for 40 microseconds, but I was having problems. The 6502s would work for a while, but the Apple would eventually stop working. I always had to have a new 6502 in my pocket in case it happened.
S. You mean the 6502 operated for 25 cycles, then the video display operated for 40 cycles?
W. That's right. When I designed the Apple II, dynamic RAM was just becoming available that could be accessed at two Megahertz. When it did become available, I changed the design of the Apple II to take advantage of it. I've told Synertek about the problem but they haven't changed their specification. New 6502s can be stopped for 40 microseconds, but they deteriorate. They are dynamic devices that store data in internal capacitive elements. As the 6502 wears in, its capacitive elements become less efficient.
S. I'm very glad you bought this up. Descriptions in my book are very vague about how long you could stop the 6502 during DMA. The data sheets are inconsistent. Synertek says 40 microseconds, Rockwell says 10 microseconds, and MOS Technology doesn't say at all.
W. Rockwell changed theirs to 10 microseconds? That's great.
S. Do you think 10 microseconds is a good number?
W. I'd stick with five or six. That's what Microsoft uses on their Z80 Softcard. It refreshes the 6502 every few cycles to keep it active. The 6502 is still used for things like disk I/O, even when the Z80 card is activated.
As with most NMOS processors, the NMOS versions of the 6502 (and even earlier CMOS versions) do not have a static core.
Neither is true. Being static or not is not a feature of NMOS vs. CMOS design, but the way individual chips are designed. In case of the NMOS 6502 it's non static nature is due the way line precharge is used to generate constant values used for certain operations. See this answer for more details.
This never applied to CMOS version, as there a precharge can not be used the same way. After all, switching both ways instant, without running much current, is the primary idea here. All CMOS versions feature full fledged constant value generators active during the whole cycle.
Thus, if you run the clock too slowly or stop the clock for too long while doing clock stretching, internal latches will lose their data and the 6502 won't work properly.
It's not about latches, but precharged lines, as the NMOS 6502 design simply spares dedicated latches wherever possible.
For how long could you stop the clock on a 6502 without running into problems?
This depends on internal bus design as well as manufacturing process, its improvement over time - plus a rather wide variety per unit - as the main influence is the quality of the charging resistors (*1).
Basically each data sheets value for clock duration can be used as guideline (*2).
(Taken from the MOS May 1976 data sheet)
For the NMOS 6500 the cycle duration is specified as 1 µs minimum and 10 µs maximum. At first sight this could mean that it can be held for 10 µs (*3). But since the critical stretch is the PHI2 high section (Rising edge to falling of PHI2), and no further qualifier is given for that, it may depend on the signal assumed. While the manual refers multiple times to a symmetric clock, the datasheet doesn't give a direct description it- But all NMOS data sheets define PHI1 high and PHI2 high is of the same Length as PHI0 high, with only a small variation allowed. Together this would allow either interpretation, whereas staying on the safe side means the clock is only within spec if held in either state for a maximum 5 µs (half the cycle time).
And this is were Woz went wrong about timing and Synertek's 40 µs. Here the April 1979 data sheet states:
The sheet doesn't say it can be stopped for 40 µs, but the maximum cycle time to be 40 µs. Like with the MOS manuals Synertek ones assume a symmetric 50/50 duty cycle for the clock. But unlike the MOS data sheet, the Synertek one links PHI1 and PHI2 pulse width directly to PHI0 puls length, thus requiring a symmetric clock. Woz' clock circuit, as used in the Apple II does not hold up to this. Based on these values, the maximum guaranteed duration to stop the clock in either state is 20 µs, not 40 as Woz assumed. There was no reason for Synertek to change the date sheet values, as his application was out of spec.
Next, Rockwell didn't change the data sheet as implied, but the 10 µs are stated already in the very first Rockwell data sheets (although I say this part is more of a misunderstanding how the interview went).
Lastly, the Z80 Softcard does not let the 6502 go for a cycle every few (5-6) cycles, but every M1 cycle, which can be anywhere between four Z80 (two 6502 (*4)) cycles in case of a NOP or 19 cycles for EX (SP),HL (*5). The 6502 thus will therefore be stopped at a varying rate between 2 and and 10 cycles.
While this is technically already outside the spec, it makes the Z80 card a great empirical evidence that any NMOS 6502 can be held for 9 µs (*6), as it did work quite well in millions of Apple II or clones.
Lessons to learn here:
*1 - Nicely shown due the fact that the minimum clock period is the same for 1, 2 or 3 MHz parts.
*2 - Interestingly the very first data sheet and manuals don't give a maximum clock duration, only a minimum, which could lead to the false assumption of a static CPU. Likewise Rockwell's papers.
*3 - Which for all practical use can be done without problems.
*4 - The Softcard runs at double the 6502 clock speed, so two Z80 cycles will make a 6502 cycle, with them being synchronized at every memory cycle (including refresh), so effective speed varies.
*5 - For Z80 specialists: Yes, the EX (SP),IX takes 23 cycles, but there also 'only' 19 cycles between M1, as its prefix is its own M1 cycle, letting the 6502 go for a cycle. In fakt, the rather weird double prefix instructions with offset like RRC (IX+d) feature three M1 cycles, thus turning off the 6502 only for a maximum of 6 cycles.
*6 - Followed by a full 1 µs cycle. It effectively creating a a 1:19 (0,5µs:19,5µs) signal form at 100 kHz, which does work reliable.
The answer to this is unknown. Test your particular part under a variety of conditions (over all possible temperature, voltage, duty cycle, IO loading ranges, etc.) to get a better guess. But who knows how representative your sample is?
Back then, the tools and NMOS processes were not characterized well enough for the total leakage of a circuit the size of a 6502 to be more than an educated wild guess at some point on a statistical distribution based on some crude (by todays standards) models. Chip tester time back then was likely too valuable to specifically test this parameter. So any timing derived from the data sheet for this parameter was probably just a good guess that turned out to be successful enough to not to require the data sheet(s) to be revised.
