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Why did the design need to reserve one channel for cascade, how did it work and what exactly was going on there?

  • In-built DMA controller was slow and hardly used on early PC's. Soundblaster and FDD are the only common usage I'm aware of. – Brian H Apr 19 at 19:44
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One of the DMA controllers is the master and the other slave. They use the cascade channel to pass on requests in order to synchronize their operation and priorities. Basically the chip with 8-bit DMA channels 0..3 has to request permission to do a DMA cycle from the DMA chip with channels 4..7, which in turn asks the chipset and CPU for permission to perform a DMA cycle.

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  • Why would DMACs need a channel to arbitrate bus access? I guess they would need to deal with ISA cards accesses anyways and no channel is needed for that – tuomas Apr 20 at 9:45
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    That's how these DMA chips work. They support cascading the chips for adding more channels. Only one can be the first level DMA controller, connected to the CPU with HRQ and HLDA signals. The channels that have a second level chip must be set to Cascade mode, so DREQ and DACK pins of the first level chip change to HRQ and HLDA of the second level chip. Basically the first chip can have four slaves, and the slave chips could have slave chips too. Sure there might have been other ways to arbitrate between DMA controller requests and grants, but chips can be cascaded. – Justme Apr 20 at 10:04
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The original IBM PC and PC/XT used just one 8237 DMA controller; with PC/AT, that was found to be insufficient. PC/AT also introduced a 16-bit extension to the originally 8-bit ISA bus, so the extension could also accomodate new IRQ and DMA signals.

PC/AT was designed with two DMA controllers, but as another-dave said, the CPU had provision for connecting just one, and the designers wanted PC/AT to be able to use PC/XT software and ISA expansion cards, and so the cascade arrangement was developed.

The second controller was responsible for the new DMA channels (#4 .. #7) and the first one (channels #0 .. #3) was made subordinate to it. Instead of signaling the CPU directly when a DMA bus cycle was needed, the first DMA controller now signaled the second one on channel #4, and the second controller signaled the CPU in turn. For channels #5 .. #7, the second controller just signaled the CPU directly.

This arrangement slightly favored the new DMA channels which were available for the 16-bit ISA cards only. In addition, the DMA channel #0, which was reserved for RAM refresh in original PC design was no longer needed for that role, and was made available in PC/AT's 16-bit extension of the ISA bus also.

In PC/XT the DMA channels #2 and #3 were reserved for floppy and HDD controllers respectively, and so the change was mostly handled by the new PC/AT BIOS. Only 8-bit add-on cards designed for PC/XT and older and using the DMA channel #1 would need updated drivers for PC/AT.

The 8237 / 8257 DMA controllers could only access a maximum of 16 MiB of memory, and when the typical amount of memory in PCs grew significantly beyond that, these traditional DMA controllers were no longer very useful.

With e.g. 32 MiB of RAM, a DMA transfer to an arbitrary memory location would have only a 50% possibility of being in the "DMA zone". If it was outside the zone, the DMA transfer would need to happen first to a buffer in the DMA zone, and then the CPU would need to be used to transfer the data to its final location outside the DMA zone, which would negate the benefit of DMA. Also, as Brian H mentioned in the question comments, these DMA controllers were slow, especially when PCI and newer, faster bus types became available.

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    Inaccurate. You are mixing how the IRQ controllers are chained via IRQ2. DMA controllers are chained via DMA4 channel. DMA channels 0..3 request DMA via DMA4. That is why DMA4 is not available on bus, all others (0,1,2,3,5,6,7) are available. – Justme Apr 20 at 7:34
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    @Justme Indeed, I misremembered. Edited. – telcoM Apr 20 at 7:57
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The 8237 DMA controller supported 4 channels. That's not sufficient for a reasonably well-appointed PC. So, you have two DMA controllers. But there's only provision to connect one controller to the CPU, so the second controller has to connect to the first one.

Typical DMA requirements:

  • Floppy controller
  • Parallel port (in some modes)
  • Sound card
  • Some disk controllers (without onboard DMA)
  • Network card
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  • I know there is only one pin for requesting bus access from the CPU, but I'm assuming ISA cards would use the same pin for bus mastering without any involvement from DMAC, so I can't see why this wouldn't work with DMA controllers as well. There would have to be some arbitration between the controllers but also I guess that could happen without reserving a channel. – tuomas Apr 20 at 9:24
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    @tuomas: Arbitration would be a solution, correct. But it's not the chosen solution. – MSalters Apr 20 at 13:41
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    An 8-channel controller would also have been a solution :-) – another-dave Apr 20 at 16:43
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    @tuomas DMA using the 8257 isn't bus mastering. The card doesn't control the DMA transfer, the 8257 on the motherboard does. The DMA controller determines what memory address are being accessed, the card just takes data from the bus or puts data on the bus on each DMA cycle. A separate DMA request line is necessary for each card for the controller to know what address the card is supposed to be accessing. Very few the ISA cards used bus mastering DMA where the card determined which memory addresses are being accessed. – Ross Ridge Apr 20 at 17:12
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    @RossRidge: Incidentally, that was the right architecture that was since abandoned at the cost of complete loss of security against malicious or buggy devices, and only later patched up with IOMMUs... – R.. GitHub STOP HELPING ICE Apr 20 at 21:22

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