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The KDF9 (English Electric, 1963) had a hardware option for timesharing. This provided four instances of most per-program context: the nest (16-deep expression evaluation stack), the subroutine jump nest (16-deep return address stack), and the 16 Q-stores (modifier/counter registers).

The timesharing director (=operating system kernel) therefore supported up to 4, no more, concurrently executing programs. Context switching avoided the need to save and restore 48 registers. So, context switching was relatively cheap for such a sophisticated machine (unless you were paying to buy the hardware). Each of the 4 possible programs had an associated priority, and completion of I/O by the hardware was cognizant of whether the completed I/O belonged to a higher priority level than the currently-executing program.

I don't think I've ever heard of any other system that provided this level of timesharing support in hardware. The ICL 1900 system sort-of comes close, in that the resident exec had a small and fixed limit on multiprogramming, but I think that's due to exec storage limits (tables take space).

These days, of course, 4 processes is indistinguishable from zero, but 4 wasn't necessarily a huge barrier in the 1960s (KDF9 had 32Kwords memory, max, so you're not fitting too much in there).

Anyway: what other systems had hardware per-program resource replication?

(Apologies for another list-oriented question, but quite frankly, the discussions that ensue from such forms is more interesting than the "here's a question, here's the answer" format. It's in the nature of historical information that people know different corners of the subject.)


Wikipedia's page on the Ferranti Orion lists a handful of computers, including the Orion, that had 'hardware support for timesharing', but it's not clear to me whether that included replicated hardware. Maybe there was nothing to replicate -- the Orion accumulators were just the first 64 words of (relocated per program) address space. The minimal requirement for hardware-assistend timesharing support may be limited to provision of datum/limit registers.

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    Well, the format is the one we have. So while don't think I got an answer, I would like to mention a series of /370 compatible mainframes by Siemens with a design somewhat alike. It featured a system of 4 levels, each with its own register set. While low end models emulated separate register sets in RAM, upper end implementations featured 4 register sets in hardware. Execution was strictly by priority. Usage was rather intended for OS support, so P1 was used for all user programs, P2 executed the OS, P3 managed I/O while P4 handled 'serious' interrupts (everything except OS calls and I/O). – Raffzahn Apr 24 at 0:47
  • "The ICL 1900 system" - I believe this came from the original Canadian design, the FP6000, which was deliberately designed to the same underlying concept as the KDF as I understand it. – Maury Markowitz Apr 24 at 2:08
  • I think the FP-6000 got it from the Ferranti Orion (which happens to use magnetic-amplifier logic like the KDF9, for whatever that is worth). – another-dave Apr 24 at 2:18
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The design you have described is very similar to Barrel processor where CPU contexts are duplicated and switched at each clock cycle.

A barrel processor is a CPU that switches between threads of execution on every cycle. This CPU design technique is also known as "interleaved" or "fine-grained" temporal multithreading. Unlike simultaneous multithreading in modern superscalar architectures, it generally does not allow execution of multiple instructions in one cycle.

Like preemptive multitasking, each thread of execution is assigned its own program counter and other hardware registers (each thread's architectural state). A barrel processor can guarantee that each thread will execute one instruction every n cycles, unlike a preemptive multitasking machine, that typically runs one thread of execution for tens of millions of cycles, while all other threads wait their turn.

Notable examples include:

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  • The CDC6000 described in more detail in the wikipedia article is probably the best example here, as it was contemporary with the system mentioned in the question. – occipita Apr 24 at 7:34
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    Right - "barrel processor" automatically associates to "CDC 6600 PPUs" in my head. This is an interesting answer to my question, not one that occurred to me. – another-dave Apr 24 at 11:25
  • @occipita Updated the answer. The question specifically asked for 20th century machines but CMOS and Niagara are both 21st century creations. – user3528438 Apr 24 at 16:33
  • You can add the Xerox Alto, which had a 16 barrel CPU for microinstructions (which were used both for implementing the actual ISA, and for I/O tasks). – dirkt Apr 24 at 18:28

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