From the schematics, I can see this uses a single RAM bank, opposed to the original Sinclair machine, which uses two separate RAM banks.
That means that the entire RAM address space must be shared between the video circuit and the CPU, while the original Sinclair machine only shared 16KB of RAM. Now, it happens that DRAMs are not only refreshed using RAS only refresh cycles (the usual way), but with regular read cycles. As the video circuit must access RAM in a semi-sequential pattern in order to build the screen, that process also refreshes memory. Let's see how:
We will assume that the video circuit reads one the bitmap area every 1.143us (i.e. 7 MHz pixel clock, and a byte holds 8 pixels, so a new bitmap byte is needed every 8 periods of the pixel clock). Let's forget about the attribute byte for the moment. To read the video memory for the first scan, it must read 32 consecutive memory addresses in 36.57us. That is, bits A0 to A4 change while bits A5 to A14 doesn't during this time. Multiplexers are wired so the low address part is used as row address and the high address is used as column address. That means that consecutive accesses hit consecutive row files. During a scanline read, 32 DRAM rows are refreshed in this time. The remaining time, up to 64us (the duration of a scanline in PAL), the video circuit is generating border or blanking signals, and no memory is read.
Scans 0 to 7 use the same row address, as these scans are spaced by 256 bytes. To read the second scanline, the high address byte is incremented, while the low address byte is the same as in scan 0. The same goes for scan 1, scan 2, etc, until scan 7. Low address byte goes from 0 to 31 (dec)
Scans 8 to 15 belong to the next character position. These scans share the same value for bits A15-A8, while A7 to A0 go now from 32 to 63.
Scans 16 to 23 use values for A7-A0 ranging from 64 to 95.
You will see that the complete row space is scanned as the video circuit finishes reading scan 56.
56 scanlines, along with border and blanking, last 56*64=3.584 ms, that's just under the limit of 4ms.
This pattern is repeated three more times: for scans 64 to 127, and again from 128 to 191. After that, there is an interval of time in which RAM is not actively read by the video circuit. For a PAL Spectrum, this interval goes from scanline 192 to 311. That's about 7.7 ms. Too much time without refreshing. During this "void" time, RAM refreshing solely depends upon the Z80 to continue accessing memory. That means that a halted Z80 might cause some RAM corruption. In practice, I've found that much more than a few miliseconds of a halted Z80 are needed to produce noticeable RAM corruption (about 2-3 minutes in a standard Sinclair Spectrum 48K!)
In fact, it's the same technique the Sinclair Spectrum uses to refresh the low memory bank. In the issue 2 model, signal RFSH was still used, but starting with issue 3, the RFSH signal was removed as it was not actually needed.