In Paul Malvino's "Digital Computer Electronics", he labeled 3 theoretical microcomputers which he called the SAPs or "Simple As Possible"s. The point of these 8-bit microcomputers was to teach computer nerds like myself how a computer really works. Just in case you haven't heard of these, I will put a description of each one below(The maximum clock speed for all of these is around 1MHz, because these are all made of 74ls components, so i wont put that down).


  • Can access 16 bytes of memory

  • 5 instructions(LDA, ADD, SUB, OUT, HLT)

  • No jump or branch instructions

  • No stack

  • No subroutines

  • No flags

  • 2 general purpose registers

  • No I/O ports


  • Can access 64 kilobytes of memory

  • 42 instructions(includes jump and branch instructions)

  • Subroutines

  • 2 flags(Sign and Zero)

  • 4 general purpose registers

  • 2 input ports and 2 output ports

  • No stack


  • Can access 64 kilobytes of memory

  • Around 50 or 60 instructions(includes jump and branch instructions)

  • Subroutines

  • 4 flags(Sign, Zero, Carry, and Parity)

  • 8 general purpose registers

  • Includes a stack

  • (I dont know how many i/o ports this has because I havent read the whole book yet)

Okay, back to my question. How do these microcomputers "stack" up against retro-age microprocessors and microcomputers like the 6502, Z80, 8080 or 8085? Are the SAP microcomputers hopelessly outclassed by the real microprocessors or do they compete or even surpass them in efficiency and viability?

  • 3
    You could probably make a table to compare them in something like 20 minutes, using the Wikipedia entries for those processors and some early computers that used them. There'd be some fuzziness (the 6502 has only three registers, only one of which is general purpose, but it's got a 256 byte zero page; are ports meaningful, or do you go for memory mapped I/O); and there'd be some headscratching (you can't have subroutines without a stack, and you can implement a software stack on any machine); but in the end, you'd place them all somewhere between SAP-2 and SAP-3. Apr 29, 2020 at 22:09
  • So SAP-2 and SAP-3 are similar to the Z80, 8080, and 6502 in performance, so if you swapped a 6502 inside, say, an Apple 2 or some other early microcomputer, with a SAP-3, would it work fine or would it struggle?
    – Nip Dip
    Apr 30, 2020 at 2:46
  • 2
    I'd argue SAP-1 isn't a computer at all. It's certainly not Turing complete.
    – tobiasvl
    Apr 30, 2020 at 8:03
  • 1
    Maybe compare with Donald Knuth's MIX? Apr 30, 2020 at 16:29
  • MIX wasn't in any sense a microcomputer though; it was designed in the age (and style) of machines that filled a room. The model numbers used to derive 1009 demonstrate that.
    – dave
    May 2, 2020 at 19:37

4 Answers 4


There is no way to establish a classification of 'efficiency' (whatever 'viability' is supposed to be) with the information given. The characterisations given, like

  • Number of Registers,
  • Number of flags
  • Memory addressing range
  • Number of instructions
  • etc.

bear no hint about performance at all. More or less registers, flags or instructions are not per se better or worse. Not even address range is. Even for a rough classification way more information would be needed. Adding some clock rate (*1) would as well not add any clarity, as clock rate itself bears no hint about performance.

The classic 6500 vs 8080/Z80 comparisons shows all of the futility of this approach: Both use a comparable technology, but differ in almost all areas mentioned above (number of registers/flags/IO ports/instructions/instruction set structure/stack/clock rate). Still, they end up in the pretty much same performance area.

Bottom line, these designs are about complexity of implementation within the context of the book. Any comparison with other implementation needs a close look of way more details as well as real world tasks to compare them.

*1 - Beein made of standard TTL does not limit them at 1 MHz, as sustainable clock rate is way more defined due the design (longest path) than the technology used.


Partial answer for SAP-1: No.

It sounds like SAP-1 has no way to load the program counter, other than incrementing for the next instruction. There are no jumps, no branches, and no way to use the PC as the destination register for an operation. Not even self-modifying code will change the program counter. But the real 8-bit microprocessors can do jumps and branches.

SAP-1 is clearly intended to be a "beginner" design. If you can't build it, you probably cannot build something better.

  • 1
    Yes, that is what the SAP-1 was built for, to be a beginner computer. I just finished building it in Logisim actually. The SAP-2 and SAP-3 are what I'm really intrigued about. Can you compare microprocessors with those?
    – Nip Dip
    Apr 30, 2020 at 2:42
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    For the others, I agree with Raffzahn's answer (which I have upvoted). There are too many differences which prevent a meaningful comparison.
    – DrSheldon
    Apr 30, 2020 at 2:50
  • Hmm, Even with SAP-1 there is not enough information to judge. For one, it's not mentioned if program storage is part of memory or not. Also, it will have a way to start, like a reset, so there's a limited jump, further, if program storage is cyclic, a loop exists by having the PC run over. Now all we need is a way to nullify results (decision making) to make it Turing complete. Anecdotal story: I once had a pocket calculator with some 40 steps and a single jump target at program start. Still one could implement a number guessing game with graphical display (to low, to high, win) :)
    – Raffzahn
    Apr 30, 2020 at 10:49
  • @Raffzahn - the referenced book has a complete description including schematic for SAP-1, and a PDF is easily located via a google search. Instructions are stored in memory, however there is no conditional execution.
    – occipita
    May 1, 2020 at 9:54
  • @occipita It's not realy usable if not in the question, isn't it?
    – Raffzahn
    May 1, 2020 at 9:56

This answer is based on a quick read of the book in question, but is likely not exhaustive. There may well be other flaws that I have not noticed.


This is a very primitive system, which in many respects cannot even be considered a real computer. It lacks any form of conditional execution, which means it is unable to implement even the most primitive algorithms. It could be used as a primitive calculator, but for no applications more demanding than this. Incidentally, this processor is likely to run much faster than the 1MHz cited -- I'd be suprised if it couldn't run at up to 5MHz if carefully assembled. The most complex path in the system is likely to be the ALU (which consists of a pair of 74LS83s wired for ripple carry, and a set of XOR gates on one input to allow negation), which has a worst case propagation delay of around 70ns. This allows 30ns for instruction decoding (which is done in fixed logic, so should be fast) and latch setup time, assuming the clock has a 50/50 duty cycle and the result is needed in half a cycle (which seems to be true).


This system is far more advanced than SAP-1, but still has a number of shortcomings. Notably:

  • There are no instructions that perform indexed addressing, which would make writing many classes of application impossible (at least without resorting to tricks like self-modifying code)
  • The lack of a call stack makes any but trivial uses of subroutines impossible - no recursive routines are possible, and each routine must have a dedicated memory location to store its return address, which would be somewhat wasteful.
  • There is no carry flag, which means arithmetic with greater than 8 bit values will be difficult and very slow.

Performance wise, its speed is likely limited by the microcode ROM (which, presumably, is an EPROM with typical access times of 450ns -- I'm just guessing here because I can't find a schematic of this design), but on a per-cycle level the design is reasonably efficient -- it has a full 8-bit ALU, not the 4-bit system of (eg) the Z80. I'd expect performance of roughly half the speed of a 6502 at the same clock rate.


This is a much more complete system. Its design is a clear imitation of the design of the Intel 8080, and has a similar feature set. Its per-clock-cycle efficiency is a little higher than the 8080's, but due to the 1MHz limit (again likely imposed by the use of an EPROM for microcode storage) is somewhat slower overall.

Its primary shortcomings in contrast to the 8080 are:

  • No addressable I/O port system. I/O is either via the restricted number of built-in ports or would need to be memory mapped (although most non-Intel processors got by with the latter anyway, so this probably isn't a serious issue)
  • No support for interrupts. This is a seriois shortcoming that would limit its usefulness in real world applications, preventing many kinds of IO device from being used and making preemptive multitasking or other operations that require a timer impossible.

Still, this is a nearly complete processor, and its not hard to see how it could be evolved into a complete system with a step of a similar size to that between SAP-2 and SAP-3.

For both SAP-2 and SAP-3 switching microcode into a higher performance medium (eg using a mask ROM or some kind of PLA) would allow them to run much faster, likely exceeding the performance of low cost microprocessors like the 8080/Z80/6502. The use of 74LSxxx chips is not an issue here - many minicomputers of the 70s and 80s used them for systems with much better performance than these microprocessors, and often had similar architectures to the ones described.

  • I definitely agree. The point of the SAP-3 after all was to be upward-compatible with the 8085. In fact, I'm thinking of adding some other microcomputers I made up to the list, like the "SAP-1.5", a modified SAP-1 with jump instructions and increment/decrement instructions, and possible a "SAP-2.5" and "SAP-0" as well.
    – Nip Dip
    May 1, 2020 at 19:50

I'll give you a brief description of the 6502 in similar terms:

  • Can access 64KB of memory (16-bit addresses) on an 8-bit data bus.
  • 13 distinct ALU operations, plus load, store and branch, each with several addressing modes. This maps to a couple of hundred opcodes, depending on which version of the 6502 you consider.
  • Subroutines and Interrupts (both maskable and not).
  • Six status flags: Negative, oVerflow, Decimal, Interrupt mask, Zero, Carry. Four of these are outputs from the ALU, the other two are for controlling the CPU's operation.
  • One accumulator (A) and 2 index registers (X,Y), 8-bits each. The index registers have limited ALU operations available, and are intended for counting and addressing.
  • I/O is memory mapped. The CPU can be paused to wait for a slow device.
  • Stack is a 256 byte fixed area of memory.

The 13 ALU operations I'm thinking of are:

  • Add with Carry (ADC)
  • Subtract with Carry (SBC)
  • Arithmetic Compare (CMP)
  • Logical Compare (BIT)
  • Logical AND
  • Logical OR
  • Logical XOR
  • Increment
  • Decrement
  • Shift Left (ASL)
  • Rotate Left (ROL)
  • Shift Right (LSR)
  • Rotate Right (ROR)

The available addressing modes are also important, but I'll simply note that the six principal ALU operations (and LDA/STA) each have access to a common set of at least 8 addressing modes, including indirect and indexed modes.


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