This answer is based on a quick read of the book in question, but is likely not exhaustive. There may well be other flaws that I have not noticed.
This is a very primitive system, which in many respects cannot even be considered a real computer. It lacks any form of conditional execution, which means it is unable to implement even the most primitive algorithms. It could be used as a primitive calculator, but for no applications more demanding than this. Incidentally, this processor is likely to run much faster than the 1MHz cited -- I'd be suprised if it couldn't run at up to 5MHz if carefully assembled. The most complex path in the system is likely to be the ALU (which consists of a pair of 74LS83s wired for ripple carry, and a set of XOR gates on one input to allow negation), which has a worst case propagation delay of around 70ns. This allows 30ns for instruction decoding (which is done in fixed logic, so should be fast) and latch setup time, assuming the clock has a 50/50 duty cycle and the result is needed in half a cycle (which seems to be true).
This system is far more advanced than SAP-1, but still has a number of shortcomings. Notably:
- There are no instructions that perform indexed addressing, which would make writing many classes of application impossible (at least without resorting to tricks like self-modifying code)
- The lack of a call stack makes any but trivial uses of subroutines impossible - no recursive routines are possible, and each routine must have a dedicated memory location to store its return address, which would be somewhat wasteful.
- There is no carry flag, which means arithmetic with greater than 8 bit values will be difficult and very slow.
Performance wise, its speed is likely limited by the microcode ROM (which, presumably, is an EPROM with typical access times of 450ns -- I'm just guessing here because I can't find a schematic of this design), but on a per-cycle level the design is reasonably efficient -- it has a full 8-bit ALU, not the 4-bit system of (eg) the Z80. I'd expect performance of roughly half the speed of a 6502 at the same clock rate.
This is a much more complete system. Its design is a clear imitation of the design of the Intel 8080, and has a similar feature set. Its per-clock-cycle efficiency is a little higher than the 8080's, but due to the 1MHz limit (again likely imposed by the use of an EPROM for microcode storage) is somewhat slower overall.
Its primary shortcomings in contrast to the 8080 are:
- No addressable I/O port system. I/O is either via the restricted number of built-in ports or would need to be memory mapped (although most non-Intel processors got by with the latter anyway, so this probably isn't a serious issue)
- No support for interrupts. This is a seriois shortcoming that would limit its usefulness in real world applications, preventing many kinds of IO device from being used and making preemptive multitasking or other operations that require a timer impossible.
Still, this is a nearly complete processor, and its not hard to see how it could be evolved into a complete system with a step of a similar size to that between SAP-2 and SAP-3.
For both SAP-2 and SAP-3 switching microcode into a higher performance medium (eg using a mask ROM or some kind of PLA) would allow them to run much faster, likely exceeding the performance of low cost microprocessors like the 8080/Z80/6502. The use of 74LSxxx chips is not an issue here - many minicomputers of the 70s and 80s used them for systems with much better performance than these microprocessors, and often had similar architectures to the ones described.