From what I understand of this answer, the Leningrad delays the Z80 during the M1 cycle so that the video generation circuitry can do its thing.
I can see how M1 is "latched" (don't know if that's the right term) into a D flip flop (it's D9 on the schematic below) when the CPU wants to read from DRAM. I think this means that /WAIT is only low for exactly one M-cycle after an opcode fetch from DRAM, and is high at all other times.
I can see how /WRBUF also influences /WAIT somehow. (I think this signal is false for two pixels, true for two pixels, and then false for another four pixels, per character cell, but I don't know why yet) It's fed to the same flip flop but I don't see what it does, so it's possible I'm wrong in my assumption in the previous paragraph about when /WAIT is low.
The difficulty I have with understanding this setup is that the pixel shift register is unconditionally loaded with each rising edge of H1. It's known that an instruction may take any number of T-states (between 4 and 23 apparently, but this does not take into account repeated prefixes), which means that H1 may happen any number of times during an instruction that's executing from RAM. Where has my reasoning gone wrong?