From what I understand of this answer, the Leningrad delays the Z80 during the M1 cycle so that the video generation circuitry can do its thing.

I can see how M1 is "latched" (don't know if that's the right term) into a D flip flop (it's D9 on the schematic below) when the CPU wants to read from DRAM. I think this means that /WAIT is only low for exactly one M-cycle after an opcode fetch from DRAM, and is high at all other times.

I can see how /WRBUF also influences /WAIT somehow. (I think this signal is false for two pixels, true for two pixels, and then false for another four pixels, per character cell, but I don't know why yet) It's fed to the same flip flop but I don't see what it does, so it's possible I'm wrong in my assumption in the previous paragraph about when /WAIT is low.

The difficulty I have with understanding this setup is that the pixel shift register is unconditionally loaded with each rising edge of H1. It's known that an instruction may take any number of T-states (between 4 and 23 apparently, but this does not take into account repeated prefixes), which means that H1 may happen any number of times during an instruction that's executing from RAM. Where has my reasoning gone wrong?

enter image description here

1 Answer 1


The ideas behind:

  1. DRAM access takes place at every CPU cycle.
  2. Every other DRAM access (or slot) is for video (further differing between attribute and pixel reads), the rest slots are for CPU. In fact, CPU and video slots simply follow each other in a rigid sequence.
  3. As the M1 read signals are active for only 1.5 clocks, the Leningrad phases or 'aligns' each M1 access into the DRAM CPU slot, if it happens to be out of phase. It is made by shortly applying the /WAIT signal for a single clock cycle.
  4. In contrary, plain memory reads or writes always last for 2 clocks, thus no need for their 'aligning'.

As a result, one says that on Leningrad, all instruction clock numbers are 'even', in the sense that if previous instruction ends at 'odd' cycle, the next one will be added a single wait clock, thus effectively making the previous instruction's number of clocks 'even'.

This interpretation is rather descriptive, however not completely correct. There are instructions that have non-consecutive M1 cycles that separated by a memory read. One example is SET 0,[ix+n], where the first two opcodes are 0xCB and 0xDD (the first one, 0xCB will be 'aligned' if needed, and the second is always 'aligned'), then there follows a plain memory read for a displacement, then another opcode, that now is always 'unaligned', thus causing another 'alignment'.

You must log in to answer this question.

Not the answer you're looking for? Browse other questions tagged .