5

The Galaksija has a 6 bit latch used for various bits and bobs, notably the part of the scanline counter which contributes to character generation, but also, it has a bit for clamping A7 high, and this bit is active low.

The portion of the schematic relevant to the question is highlighted in red:

Annotated schematic

Imagine the whole address space is chopped into blocks 128 bytes long. This will have the effect of mirroring every odd-numbered block to the preceding even-numbered block. I can imagine that this would be useful for refreshing some rare kind of DRAM, but this is not used in the Galaksija. So what does the Galaksija use the A7 clamp for?

Datasheets:

  • Mind to add schmatics or at least a circuit description? – Raffzahn Jun 16 at 21:54
  • 1
    Based on my reading of a partial schematic I found, the MSB of the latch is indeed used to gate the A7 line to the RAM only. It's SRAM, so no refresh required, but the refresh circuitry of the CPU is apparently used to assist the video output (ZX81 style). It's obviously a deliberate feature but I don't know why. – Chromatix Jun 17 at 4:14
  • I feel like I'm playing ADVENT looking at that schematic... – Alex Hajnal Jun 17 at 9:05
  • Thanks for the edit @AlexHajnal! Much better. – OmarL Jun 17 at 9:37
  • The original schematic is at retrospec.sgn.net/users/tomcat/Galaksija/MagScans/RACUN01/…, but doesn't seem to clarify matters. I can't read Serbian, but AFAICT the surrounding article text contains no reference to it. – occipita Jun 17 at 10:00
4

This is not intended to be a full answer; it's just my take on what the hardware is doing.

Note: There are undoubtedly errors below.

The description below follows all of the signals that feed in to A7. It should make sense when read from top to bottom.

U10 : 74139 dual 1-of-4 demux ("Address decoder")

Outputs default H.

Left side on schematic:

A15 = /Enable

A13=L, A14=L, A15=L ⇒ /CS_ROM = L
A13=H, A14=L, A15=L ⇒ /Enable on the chip's other demux = L.
                      Also connects to /CE2 on the RAM via several NOT 
                      and NAND gates.  
                      The additional gates also hook into the output
                      of the other half of this gate and the Z80's 
                      refresh line (used for the video circuitry).
Other two outputs unused.

Right side on schematic:

A13=H, A14=L, A15=L ⇒ /Enable = L (as described above)

A11=L, A12=L, /Enable=L ⇒ Latch/Kbd(?) CS = L
                          This output also hooks into the afore-
                          mentioned circuitry hooked up to the RAM's
                          CE2 line.
Other three outputs unused.

U6 : 74251 1-of-8 multiplexer

This appears to be used for scanning the keyboard matrix. It takes one of its inputs from one of the lines of interest but does not output to the circuit we're interested in.

This chip is one of the two chips connected to the Latch/Kbd CS line.

When Latch/Kbd CS is L then this chip's outputs are active. When it's H the outputs are high-Z.

U7 : 74138 1-of-8 Demux

This chip is one of the two chips connected to the Latch/Kbd CS line.

Outputs default H.

Only one output is of interest on this chip (Q7).

/E0 = Latch/Kbd(?) CS
/E1 = MREQ
E2  = H

A0 (chip) = A3 (on the Z-80 bus)
A1 (chip) = A4 (on the Z-80 bus)
A2 (chip) = A5 (on the Z-80 bus)

/E0=H, /E1=H, A0=H, A1=H, A5=H ⇒ Q7 = L

Or in other words:

Latch/Kbd CS=H, /MREQZ80=H, A3Z80=H, A4Z80=H, A5Z80=H ⇒ Q7 = L

U17 : 3-input NOR gate

The NOR gate's three inputs are Q7 from the U7 demux, MREQZ80, and WriteZ80.

Output is connected to the 74174 latch's /CP line.

U8 : 74174 latch

This latches the input (D2Z80..D7Z80) on the rising edge of /CP.

Inputs:
/CP : See U17, immediately above.
D0..D5 = D2Z80..D7Z80

Outputs:

Q0         → Character generator C0, Line out
Q1, Q2, Q3 → Character generator C1, C2, C3
Q4         → Line out
Q5         → U18 NAND (left)
             This is the one we're interested in.

U16 : 7400 quad 2-input NAND

One gate is simply used to invert A7Z80. The output of this, along with Q5 from the latch are fed into a second NAND gate. The output of this goes to A7 on the 6264 SRAM.

Synopsis

TBD. First guess is that it might allow the currently-pressed keyboard keys to be read directly either to the Z80 or to RAM.

| improve this answer | |
4

Like the ZX80 and ZX81, the Galaksija uses the Z80's DRAM refresh as an address generator for display generation. During refresh, the Z80 places the contents of its R register on lines A0-A6, and the I register on A8-A16, but the A7 line is always zero. Therefore, in order to generate screen memory addresses with A7 set to 1, circuitry is required to force the A7 line high. This is what this bit of the latch is used for.

Only RAM addresses are affected by this, meaning that code in ROM used to generate the correct sequence of addresses can run unimpeded.

| improve this answer | |
  • I thought it might be something obscure and stupid about the way the Z80 works. Good to see that I was right, and that I didn't have to dig into the details myself too hard. – Chromatix Jun 17 at 11:22
  • Just one nitpick: it's not the A register that's put on the address bus, but I. Other than that, R is 8 bits wide so it would have been enough to set the uppermost bit of R using ld a,r or whatever. – OmarL Jun 17 at 11:42
  • @OmarL - thanks, fixed. Got confused because the A register supplies the upper address byte during IO operations, and I just assumed it would be the same... – occipita Jun 20 at 5:59
  • @OmarL - I haven't checked the actual behaviour, but my copy of the Z80 user manual states that only bits 0-6 of the R register are placed on the bus during refresh cycles. It doesn't specify what the other bits are. Does bit 7 actually get used? If it does, did the designer perhaps not realise this? – occipita Jun 20 at 6:15

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