What new opcodes were added to Motorola MC6801/MC6803?

Background for the question, and what I've figured out so far (correct me if I'm wrong):

The Motorola MC6801 (and MC6803) had an "enhanced instruction set"; it added 10 new instructions to the MC6800's base instruction set, expanding it from 72 to 82. Reading the 6803 instruction set summary, I've found 9 new instructions: ABX, ADDD, ASLD, LDD, MUL, PULX, PUSHX, STD and SUBD.

For the tenth new instruction, it seems that ASLD can use the equivalent mnemonic LSLD (both with opcode $05). It operates on the new D register, after all, so it must be new, but it seems a little strange to count an alternative mnemonic as a "new instruction", so I might be missing something here? Especially because the summary also lists new mnemonics for the other ASL instructions (like ASLA now has the synonymous LSLA).

Curiously, the ASL instruction with the addressing mode "indexed" is listed as opcode $68, while the indexed LSL has opcode $65. I don't really understand why all the ASL/LSL mnemonics would be synonymous and have the same opcodes except the indexed one. I'll assume this is a typo, unless I'm missing something obvious here.

Of course, new instructions weren't all that was changed. New addressing modes for existing instructions were also added. At least one of them replaced an undocumented opcode on the MC6800: The infamous "HCF" instruction with opcode $9D was replaced by a JSR with direct addressing mode (as I briefly mentioned in this question).

I can look through the entire instruction set summary, checking off each opcode to find any new addressing modes, but perhaps someone here knows, or knows if there's a simple overview anywhere. And even if I have to resort to that, I can't really reconcile indexed ASL/LSL having two different opcodes, so a secondary source on that would be great either way to see if it's a typo or not.

So: Is there an overview of what new opcodes were added to this CPU, both new instructions and addressing modes?

  • 2
    @Raffzahn I haven't worked out all of them, as I don't know all the new opcodes. I don't know what the tenth new instruction is (the ASL/LSL peculiarity might solve it, but I don't understand it), nor what all of the added addressing modes are. My question is the bold one on the top, which is rephrased a little at the bottom.
    – tobiasvl
    Commented Jun 21, 2020 at 20:17
  • 2
    Keep in mind that such statements are often part of advertisement, so were is the '10 instruction' one originated?
    – Raffzahn
    Commented Jun 21, 2020 at 20:39
  • 1
    I read or watched a really good blog post or YouTube video on how "how many instructions does this CPU have" has various interpretations leading to different answers. I wish I had a link but yeah you may have already found it and the claimed number could be marketing hype picking the biggest number of all interpretations. Commented Jun 22, 2020 at 4:18
  • 3
    I found a MC6801 reference manual with exact same summary table where $65 is defined, but later on in the document, Appendix B has the opcode map, which has 220 defined opcodes. In that map, $65 is an unused opcode, and there is a list of which instruction mnemonics have the same opcode, and the list includes ASL/LSL instructions and few Branch instructions. So basically, some instructions map to identical opcodes. In light of this, ASLD and LSLD could be counted as separate instructions then, even if the opcode is same.
    – Justme
    Commented Jun 22, 2020 at 8:30
  • 1
    Found the blog post, from four years ago: How Many x86-64 Instructions Are There Anyway? Commented Jun 22, 2020 at 12:15

1 Answer 1


MC6800 supports 197 opcodes and MC6801 (and MC6803) supports 220 opcodes.

So there are 23 new opcodes defined:

  1. ABX ($3A)
  2. ADDD ($C3, $D3, $E3, $F3)
  3. ASLD ($05)
  4. BRN ($21)
  5. JSR ($9D)
  6. LDD ($CC, $DC, $EC, $FC)
  7. LSRD ($04)
  8. MUL ($3D)
  9. PSHX ($3C)
  10. PULX ($38)
  11. STD ($DD, $ED, $FD)
  12. SUBD ($83, $93, $A3, $B3)

Since JSR instruction already existed, extending the instruction with new addressing mode might, or might not be included in the list of new instructions.

The new BRN instruction, BRanch Never, is only useful during debugging when replacing other branch instructions for test purposes, so it would not be useful under normal circumstances. Hard to say if that counts as a new instruction.

Additionally, the MC6801/MC6803 manual defines new instruction mnemonics as aliases for existing mnemonics, so these will have the same opcodes:

  • BHS (alias for BCC)
  • BLO (alias for BCS)
  • LSL (alias for ASL)
  • LSLD (alias for ASLD)

Finally, they also improved the CPX instruction to update the C flag instead of just N/Z/V flags, to allow for use of all branching instructions.

In MC6801/MC6803 documentation, everything stated above are included in a list of new instructions, including the aliases, JSR, BRN, and CPX changes, but in that document they don't state a number how many new instructions there are.

  • Thank you! Perfect. This also seems to confirm that LSL having its own opcode in the summary I linked to was a typo. Based on your list I'm inclined to think BRN is the tenth new instruction, as useless as it is in actual programs.
    – tobiasvl
    Commented Jun 22, 2020 at 16:23

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