Even the Intel 4004, which had a 4-bit word size, had a 12-bit address space. I'm wondering if any commercial CPUs had an 8-bit or similar address-space for programs, data, or both.

I'm particularly curious about CPUs with small program address-spaces and the types of problems they were able to solve with such limitations. I'm slightly less but still interested in CPUs with small address-spaces for data.

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    So you're specifically looking for an 8-bit address bus? Your question seems needlessly vague; you're saying you don't "think" zero page addressing should count, but you should easily be able to exclude it from whatever criteria you're actually looking for.
    – tobiasvl
    Jul 8, 2020 at 17:10
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    Plenty of CPUs are now built with only integrated RAM that are less than 256 words. Jul 8, 2020 at 17:58
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    The 8051 had only 8 bits address space for the standard RAM; however, the address spaces for the code ROM and the external data memory were 16 bits wide. Jul 8, 2020 at 19:30
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    @Chromatix: On many microcontrollers, program code is fetched from a bus which is completely separate from the one used for data.
    – supercat
    Jul 9, 2020 at 0:04
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    @dirkt, The history of computing machinery (i.e., the topic of this forum) starts in an era when a machine with tens of addressable locations in which to store data would have been called "big," to the present, in which a machine with only a billion or so addressable locations would be unacceptably "small" for many users. Subjective judgments like, "anything moderately complex" simply have no meaning here unless you can narrow the context and say "complex" compared to what else. Jul 9, 2020 at 13:31

8 Answers 8


PIC: 7 bit address space

The Microchip PIC family of CPUs specifically the 10, 12 and 16 series have 7 bits of address space. While 7 bits is not exactly 8 bits this shows that there are commercial CPUs still on sale and still widely used that have less than 8 bit address space (they are used for example for power management on some Macs and are the most common CPU for smart cards).

However it does not meet some of your requirements because your requirements have some assumptions that does not necessarily hold for some CPU architectures.

For example, you asked about possessing an 8-bit PC. This makes several assumptions that are partly true and partly false for the PIC:

  1. The PIC is a Harvard architecture. The framing of the question has a hidden assumption of a Von-Neumann architecture where program instructions and data have the same address space. For the PIC it has a 7 bit data and 11 bit program address space. So it does not have an 8 bit PC.

  2. However, the PIC cannot process more than 8 bits of data. Therefore the PC is mapped to two separate registers. Reading from and writing to the PC is done 8 bits at a time even though the full address space is 11 bits. So processing the PC, as in accessing it, is done in 8 bits.

Even weirder CPUs

There are other architectures that fall even further from you assumptions. For example stack machines are CPUs that have 0 bit data address space. However, like the PIC, they have different program address space.

The main advantage is that you don't have to encode addresses at all in your instruction set allowing you to have very small instructions. Home-made stack machines such as Lisp or Forth machines can go down to using as few as 3 bits to encode instructions.

If you wonder how we can do computing without any addressing I suggest you look at the programming language Forth (like Lisp, the language is so simple that people have designed hardware implementations of them so it is not merely a programming language but also the instruction set for some CPUs)

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    Stack machines may well have an address space larger than 0 bits. The address isn't encoded in the instruction, but it's taken off the stack. Forth and Lisp doesn't do computing without any addressing. Jul 9, 2020 at 5:39
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    FWIW, I made something with a PIC with a 5-bit address bus. 25 bytes of RAM and 7 (IIRC) memory-mapped I/O registers. I think I used about half of the RAM. Jul 9, 2020 at 10:09
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    I thought the 8bit PIC microcontrollers had several memory banks which could be switched via a configuration register? Or is this only true for some of them?
    – Michael
    Jul 9, 2020 at 11:25
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    @LarsBrinkhoff I just wanted to show the OP that the definition of address space is not simple. If you consider addressable by instructions as I've done in my answer then CPUs can have anywhere from zero to 64 bits of address. If you consider load/store address like what's used by RISC and stack machines then they usually have address space = register size. If you consider addressable physical memory then you may need to think weather you want to consider external hardware as part of your architecture etc. More than getting points I wanted to show the variety of what is possible
    – slebetman
    Jul 9, 2020 at 14:59
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    @Michael PICs come in lots of different sizes. My one had no banking. It had a bigger brother with 2 banks (16 bytes extra) and a bigger bigger brother with 4 banks (48 bytes extra). (Only the top half of the 5-bit address space is banked) Jul 9, 2020 at 18:00

The KENBAK-1 has 256 bytes of memory. I'm not certain whether it had an 8-bit PC.


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    This is the only correct answer so far. All of the other answers try to get around the question: multiple address spaces (data space in a Harvard architecture, internal microcontroller RAM, IO space), bits of the PC not connected to pins, or multiplexing.
    – DrSheldon
    Jul 9, 2020 at 16:03

The first that comes to mind is Cypress' M8C core used in the PSOC-1 series. While it has a 16 bit program address space (and thus 16 bit jump instructions), its data as well as the register space are each strictly 8 bit.

Implementations do use up to two sets of 256 registers and may offer several sets of 256 Byte banks. From the manual:

The M8C is an 8-bit CPU with an 8-bit memory address bus. The memory address bus allows the M8C to access up to 256 bytes of SRAM,[...]

To take full advantage of the paged memory architecture of the PSoC device, several registers must be used and two CPU_F register bits must be managed.

Interrupt routines are always located in page 0, Stack by default. Data may reside in any page. Access is handeled by a set of registers:

  • CUR_PP holds the current active (default) page
  • STK_PP holds the stack page
  • IDX_PP holds the page used for all indirect address (yes, even indirect pointers are only 8 bit)
  • MVR_PP and MVW_PP hold the pages the MVI instruction operates on (MVI can do indexed memory access with pointer increment)

Two bits in the CPU flag register (*1) define the page mode:

  • No Paging (also during interrupt)
  • Indexed modes use the stack page (including stack instructions)
  • Direct mode use CUR_PP, indexed use IDX_PP
  • Direct mode use CUR_PP, indexed use STK_PP

I seriously love this CPU. It's as close as it can get to a strict 8 bit CPU while being able to solve real world tasks. It's my personal favourite for a CPU as simple as possible without getting lost in academic games (*2).

All data is always only 8 bit. All instructions carry either

  • no parameter, or
  • one parameter one holding an 8 bit address or 8 bit constant, or
  • two parameters holding either two 8 bit addresses or an address and an 8 bit constant.

The only exceptions are LONG JUMP and LONG CALL holding a 16 bit program address (yes, there's a short CALL, using only an 8 bit offset :). Programm memory access for data purpose features the only complex (one byte) instruction, with an address to be prepared in registers. Everything else is quite regular and straight on.

Despite being 8 bit and quite simple it features some of the elegance of a /360.

*1 - Which is not special but part of the register file like any other, thus accessible with all register instructions.

*2 - Not to mention the incredible versatile I/O units. In some sense configurable processors of their own!


Not strictly an answer, but some early computers had very limited addressing. The Harwell Dekatron computer, which operates entirely in decimal, has an address space of 100 words, of which 90 are RAM and the other 10 are devices. Programs for it are usually run directly from a paper tape device (where the tape, rather than the PC register, is advanced after reading each program word), but subroutines can also be loaded into RAM and run from there.

Among architectures with multiple address spaces, the Z80 has an 8-bit I/O address space which is separate from the 16-bit one used for programs and data. But this is probably not what the OP is asking for.

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    (You don't need to use the past tense for the Dekatron; it still exists, and still operates, at The National Museum Of Computing at Bletchley. You can visit, as I did, and even press a button to operate it!)
    – gidds
    Jul 9, 2020 at 10:03
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    The Z80 IO address space is actually functionally 16-bit due to the well-known (albeit originally undocumented) behaviour of placing the contents of the A register on the high address lines during all IO operations. This behaviour was used, for example, to select individual rows in the ZX Spectrum keyboard matrix. I'm not sure whether or not this also applies to the otherwise-similar Intel 8080/8085 processors, however.
    – occipita
    Jul 10, 2020 at 1:36
  • @occipita: The IN A,(C) instruction places BC on the address bus. I don't know whether anyone exploited the fact that IN A,(const8) does anything in particular with the high-order address bits, or if code for devices that use the high-order address bits always use the IN A,(C) format.
    – supercat
    Jul 10, 2020 at 19:14
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    @gidds I've updated this answer to use present tense Jul 11, 2020 at 17:50
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    @PaulHumphreys Cool. (I can't edit my comment; I'll leave it there for the links.)
    – gidds
    Jul 11, 2020 at 17:57

The Intel 8048 which was used in the Magnavox Odyssey2 had an 8-bit external address bus.

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    Only in case of data, and only early models.
    – Raffzahn
    Jul 9, 2020 at 6:30
  • The program memory of it is 4 Kb.
    – h22
    Jul 11, 2020 at 12:30

Not quite there, but close, is the VT52 text terminal with a CPU that has a 10-bit code address space. The data address space is 11 bits.

As answered by others, low end microcontrollers may well have 8-bit code and/or address spaces.

  • Do you know any more about this vt52 cpu? Jul 9, 2020 at 11:14
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    VT52 maintenance manual - schematics in chapter 4. Instruction set in table 4-1.
    – dave
    Jul 9, 2020 at 11:27
  • @OmarL I couldn't find anything in the manual to indicate it even had a "CPU" as we'd know it today. It's processing seems to have been carried out amongst several discrete logic chips. I know its successor the VT100 used an Intel 8080. Indeed modern CPU chips seem to have been originally developed for another terminal, the Datapoint 2200 Jul 9, 2020 at 11:44
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    @PaulHumphreys, it's not a microprocessor, but I do consider it a CPU. Much like mainframes and minicomputers that had processors implemented as possibly hundreds of boards in a cabinet. Jul 9, 2020 at 11:54
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    @PaulHumphreys, I agree many people now seem to equate CPU with microprocessor but it's not something I'd like to condone. A quick search turns up IBM documentation from 1955 using the term, which is long before the first microprocessor. (Incidentally "microprocessor" first meant microprogrammed processor, but I'm not arguing we bring back that definition.) Jul 9, 2020 at 12:11

The RCA 1802 CPU had only 8 address lines, which were time multiplexed to specify a 16 bit address.

It was used in "telly tennis" type game machines in the mid 1970's and early home computers like the COSMAC ELF as well as the Hubble space telescope.

Just recently my retired neighbour was regaling me with stories of when he was developing a system with two of these CPUs; One to run code in 2Kb of RAM and the other to bit-bang RS-232.

  • The address registers on the 1802 are all 16 bits wide; during every memory cycle, the chip will output the top half of an address register, hit a strobe, and then output the bottom half, so I'd call that a 16-bit address space. Interesting chip, though. Fetching a byte from any of sixteen address registers with post-increment is a one-byte two cycles instruction (as small fast as any other instruction) but loading an address register with a constant requires code totaling six bytes and eight cycles.
    – supercat
    Jul 9, 2020 at 22:17

The DEC PDP-8, a 12-bit machine with 4k words of memory, had 8-bit direct addressing (7-bit offset and a 1-bit Page Zero selector). However, an Indirect bit in the order code caused the contents of the directly addressed location to be used as a 12-bit address of the real operand. Later models of the PDP-8 family could have up to 7 more "Fields" of memory, each with 4k words, which could be addressed only indirectly, having first set the required Data Field (0-7) by means of a pseudo Input/Output Transfer (IOT) instruction.

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