The first that comes to mind is Cypress' M8C core used in the PSOC-1 series. While it has a 16 bit program address space (and thus 16 bit jump instructions), its data as well as the register space are each strictly 8 bit.
Implementations do use up to two sets of 256 registers and may offer several sets of 256 Byte banks. From the manual:
The M8C is an 8-bit CPU with an 8-bit memory address bus.
The memory address bus allows the M8C to access up to
256 bytes of SRAM,[...]
To take full advantage of the paged memory architecture of
the PSoC device, several registers must be used and two
CPU_F register bits must be managed.
Interrupt routines are always located in page 0, Stack by default. Data may reside in any page. Access is handeled by a set of registers:
- CUR_PP holds the current active (default) page
- STK_PP holds the stack page
- IDX_PP holds the page used for all indirect address (yes, even indirect pointers are only 8 bit)
- MVR_PP and MVW_PP hold the pages the MVI instruction operates on (MVI can do indexed memory access with pointer increment)
Two bits in the CPU flag register (*1) define the page mode:
- No Paging (also during interrupt)
- Indexed modes use the stack page (including stack instructions)
- Direct mode use CUR_PP, indexed use IDX_PP
- Direct mode use CUR_PP, indexed use STK_PP
I seriously love this CPU. It's as close as it can get to a strict 8 bit CPU while being able to solve real world tasks. It's my personal favourite for a CPU as simple as possible without getting lost in academic games (*2).
All data is always only 8 bit. All instructions carry either
- no parameter, or
- one parameter one holding an 8 bit address or 8 bit constant, or
- two parameters holding either two 8 bit addresses or an address and an 8 bit constant.
The only exceptions are LONG JUMP and LONG CALL holding a 16 bit program address (yes, there's a short CALL, using only an 8 bit offset :). Programm memory access for data purpose features the only complex (one byte) instruction, with an address to be prepared in registers. Everything else is quite regular and straight on.
Despite being 8 bit and quite simple it features some of the elegance of a /360.
*1 - Which is not special but part of the register file like any other, thus accessible with all register instructions.
*2 - Not to mention the incredible versatile I/O units. In some sense configurable processors of their own!