Why is the clock frequency of the PS/2 keyboard protocol so high?
I wouldn't call it high. It's quite in line with similar keyboard speeds - like Amiga operating a 17 kHz.
At 11 bits per scancode, 10 kHz is a massive 909 scancodes per second. World-record holder Barbara Blackburn peaked at 216 wpm ≈ 18 cps ≈ 54 scancodes/sec. on a Dvorak keyboard layout. Even with punctuation and modifier keys, there's still a ton of budget available.
While typing speed - and more important delay time (aka keyboard lag) - defines a lower boundary for a useful keyboard interface, it provides no argument for an upper limit. To keep latency low, the highest reliable speed is to be preferred.
But there are several issues with the number used. For one, actual English language records, using computer keyboards, are past 300 word/min or 25 char/s, which would mean 75 scancodes/s using above equation. That's already past a one per frame as many early computers did scan and past what can be done on a genuine IBM PC.
More important, the whole argument is at error, as average typing speed is exactly that, average. Levelled out over several minutes. Certain combination can be way closer to each other. Think of combinations like 'er' wich are more like a single move.
So a keyboard able to handle fast writers should go well past these number. At least double it, meaning 150 scancodes/s would make a good lower end for transmission speed. With an 11 bit word that's a 1,650 bit/s ... of course any controller will need some time to feed it, so selecting a value 2-3 times of that is applicable. It's obvious that we already get close to the 10 kBit IBM defined as lower limit.
On the PC the speed is defined by what the 8048 controller within the Keyboard can deliver, as the receiving side was a 74LS322 shift register, good for some Mbit instead :))
On the AT it was what the microcontroller in the keyboard and mainboard could do without any issue - that's BTW why there is such a wide range of 10..16 kHz, as it allows them to operate at less reliable clock sources as well.
Having recently bit-banged the PS/2 protocol on a 1MHz 6502, I feel like it sure would have been easier on keyboard port implementers if IBM had decided on a lower frequency, so we could have had some time to decode the protocol inside my interrupt handler, instead of offloading it to a circular buffer.
Why should IBM have cared about any implementation different from their own?
Did IBM provide any reasoning for the chosen frequency?
It's an obvious choice, and AFAICT artificial slowed down. In a setup with a HW shift register and a microcontroller (IBM-PC) or two microcontrollers (PC-AT), 16 kHz is a quite low rate, kept in a range of easy detection and leaving lots of room for slow controllers.