The original CHIP-8 interpreter ran on RCA 1802-based kit computers and home computers, most notably on the COSMAC VIP. Some of the CHIP-8 opcodes are complicated and involve many memory round-trips, for example the drawing instructions, or the ones that store register values in RAM. However, many of them are straightforward register-to-register operations which can be implemented fairly uniformly in a bytecode interpreter: just fetch the bytes, switch on the relevant parts of it to jump to the right operation, then do the operation.
For this second kind of "regular", "atomic" operations, I think it should be meaningful to assign a single number to the effective interpretation rate, i.e. on average restricted to these operations, how many CHIP-8 bytecode instructions could the original interpreter run per second on the COSMAC VIP?