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The Intel 8087 supported both single and double precision floating point, but only in memory; the on-chip registers were purely double precision. (Strictly speaking they were actually 80-bit extended precision.) The same is true of the Motorola 68881, designed at almost the same time. Nor was this design decision exclusive to microprocessors, or to scalar machines; Cray vector supercomputers of that era had vector registers of double precision operands.

By contrast, the later SSE2 instruction set has registers that can be treated as four single precision operands or two double precision, i.e. you can put a pair of single precision operands into the space that would've been occupied by a double precision operand. And as far as I can tell, this is typical of modern floating-point architectures, both CPU and GPU.

Why the change?

Is it for the technical reason that we now have enough transistor count to build SIMD vector units (as distinct from the Cray supercomputers which had vector registers but a scalar FPU) and that layout makes more sense for SIMD?

Is it for the business reason that nowadays graphics and machine learning provide important workloads that actually want single precision?

Or some other reason I haven't thought of?

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    There's no real workload that "wants" single precision. There are many workloads which can live with single precision, but extra precision doesn't hurt them. As you say, vector units can provide double the throughput in single precision, and that is what's desirable. – MSalters Sep 14 at 8:44
  • It's a simple size/accuracy vs speed tradeoff. Before, there was only one option. Now there are two options. – Mooing Duck Sep 14 at 16:16
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When you have a small transistor budget, it is considerably easier to design your circuitry around a single representation format - the most capable one - and treat converting other formats to and from it as a separate problem. That's how the 8087 and 68881 were both designed.

Today, there are enough transistors sloshing around in the average CPU that converting formats on the fly is trivial, and it's thus possible to pack variable numbers of floats into a single wide register. Until about the 6th-generation x86 era, that was not yet practical.

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    Incidentally, the C language was also designed around the concept that there is one kind of integer value and one kind of floating-point value. While smaller integer and floating-point containers exist, values were converted between the container types and the value types whenever they were loaded and stored. A peephole optimizer might have replaced the sequence "load "float" value from X [converting to double]; store "float" value to Y [converting from double]" to "copy float value from X to Y without conversion", but otherwise compilers used exclusively larger types. – supercat Sep 14 at 17:07
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To expand a bit on Chromatix’s great answer: if you do all calculations at the highest precision, and convert to and from that, you only need a single FPU on your chip.

When you build a floating-point VPU, you’re building multiple FPUs in parallel anyway. It’s the whole point.

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The older devices were intended primarily for high precision scientific applications.

The newer ones are intended primarily for multimedia, and don't need so many bits.

It's a similar phenomenon to how old computers from the 50s and 60s operated in words of 30~40 bits, which then got replaced by 8-bit bytes adequate for business application.

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I've seen a half-dozen different schemes for handling single vs double precision.

One extreme is to do everything in double precision and then convert to/from that format if single precision operands are used.

Another extreme is to break double-precision numbers in half and do multiple operations (that are essentially single precision) on the double-precision operands.

And there have even been processors with separate single-precision and double-precision FPUs.

Added: And I will note that microprogrammed processors could mimic several different schemes, even when working with integer ALUs.

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