2

During the execution of an IN or OUT instruction (so after the opcode and its single-byte argument have been fetched from memory), how does the Intel 8080 react to its READY pin going down? Is it meant to be possible for IO peripherals to be not immediately ready? If they are not ready, does the CPU keep the port number on the address bus?

Improve this question

1 Answer 1

Reset to default
4

(You may as well want to take a look at the manual, like p.2-5 of the September 1975 Manual)

During the execution of an IN or OUT instruction [..], how does the Intel 8080 react to its READY pin going down?

Operation is the same for all M cycles, independent of memory or I/O, as seen here:

enter image description here

(Taken from p.2-8 of the 8080 Micro Computer Systems User's Manual of September 1975, 98-153B)

  • During Phi2 of T1 of any machine cycle the 8080 will output an address on A0..15 and status information denoting the type of access on D0..7 (usually decoded into signals by a 8212 latch).

  • During Phi2 of T2 READY is sampled (*1,*2).

    • If active (Low)
      • WAIT is asserted (pulled LOW)
      • waitstates (Tw) are inserted. Waitstates are essentially repeated T2. Address signals are kept stable.
      • Ready is sampled again on Phi2 during each waitstate.

  • If inactive operation continues with T3 of whatever machine cycle is executed.

Is it meant to be possible for IO peripherals to be not immediately ready?

Yes. That's what these signals are meant for, to stretch access until a device is ready to deliver. This can be of any time, microseconds or days.

If they are not ready, does the CPU keep the port number on the address bus?

Yes. As long as Ready is asserted, the address will be stable. Still, to decide between a memory address and an I/O address the status information needs to be decoded first (during T1) to decide if it's about I/O. D4 = high is signalling an OUT instruction, while D6 = high does so for IN. Using an 8228 does simplify this by handling all the related logic.

*1 - Together with HOLD and `HALT for DMA and stopping.

*2 - Due the clock structure this happens around 2/3rd of a clock cycle.

Improve this answer
1
  • Side note: You are right that the 8080, like most other processors, can take arbitrary number of wait-states, so your days example will not harm processor operation. This is not necessarily true for mainboards, though. On th IBM PC, the whole bus is suspended while an expansion card requests wait states. As RAM refresh also uses the system bus, the PC mainboard violates refresh requirements as soon as you delay for more than 15 microseconds.
    – Michael Karcher
    Commented Sep 23, 2020 at 21:03

You must log in to answer this question.

Not the answer you're looking for? Browse other questions tagged .