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I'm trying to understand how the video hardware (CRTC and Gate Array) in Amstrad CPCs works. Specifically, I have a question about the behavior of the refresh memory addresses and row adresses output by the Motorola 6845 CRT controller during horizontal/vertical retrace.

When the horizontal counter reaches the value "Horizontal Displayed" (register 1) is the refresh memory address reset to the start of the current/next character row immediately?

I'm confused, because I read in the Datasheet for the CRTC:

Both the memory addresses and the row addresses continue to run during vertical retrace thus allowing the CRTC to provide the refresh addresses required to refresh dynamic RAMs.

I guess that would make sense for vertical retrace because the refresh memory address is reset to the value of "Display Start Address" (register 12/13) at the start of the frame anyways.

But I'm unsure what happens during horizontal retrace.

So, in other words what values do the refresh memory addresses and the row addresses have during horizontal and vertical retrace?

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2 Answers 2

Reset to default
4

Short answer from memory:

  • At the beginning of a frame the address is set to zero
  • The address is incremented over a line for R0 (total chars aka horizontal timing) character access cycles.
  • Only R1 (displayed characters) are visible.
  • The address is reset after R0 character access cycles.
  • Then the scan line counter is incremented
  • When the scan line counter reaches R9 (Max Scan Line - 1):
    • Scan line counter is reset
    • Address is incremented by R1

Rinse and repeat.

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The horizontal counter increments continuously with the CRTC clock, and the vertical counter (divided into a pixel row counter and a text line counter) increments continuously with the horizontal sync pulse. The blanking and sync signals are toggled, and the counters are reset, when these counters exactly match values set in configuration registers.

The counter resets specifically occur when the "horizontal total" and "vertical total" registers are matched. The latter also triggers reload of the address register, which is what permits hardware scrolling and double-buffering with the CRTC. The addresses continue to increment during the blanking period, as shown in the following timing diagrams from the MC6845 datasheet:

horizontal timing vertical timing

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