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In the MIPS architecture, blez/bgtz and bltz/bgez are encoded differently:

blez/bgtz are encoded as: [BLEZ/BGTZ: 6 bits] [RS: 5 bits] [0: 5 bits] [OFFSET: 16 bits]

bltz/bgez are encoded as: [REGIMM: 6 bits] [RS: 5 bits] [BLTZ/BGEZ: 5 bits] [OFFSET: 16 bits]

My question is: Why didn't they encode all 4 branches into the REGIMM space which is more than large enough to accommodate them and many more? Why waste 2 out of 64 instruction slots on blez/bgtz instead?

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    There aren't that many bits in REGIMM. Shared with conditional trap instructions, so one bit to distinguish B from T. Two more bits for And Link and Likely variants of branch. Just enough left over for BLEZ/BGTZ, but I would guess that because those two don't have the full variants that BLTZ and BGEZ do, they were added later. The MIPS designers didn't care too much about a regular instruction set if it would simplify the hardware. Oct 30, 2020 at 10:46
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    @HughFisher Would you mind to turn this into an answer instead of a comment? It already contains all relevant points.
    – Raffzahn
    Oct 30, 2020 at 13:10
  • Since I wasn't involved in the MIPS design, and for that matter have never designed a CPU instruction set, I think this is a likely guess rather than an answer. There are (I think) just enough bits that the designers could have included the two additional branches if they'd wanted to. Oct 30, 2020 at 13:17
  • @HughFisher - but conditional traps weren't there in the first version of MIPS - it was just bltz, bgez, bltzal, bgezal (source: mips IV pdf which shows encodings per vesion) - 3 bits were perfectly free for the taking back then. Oct 30, 2020 at 14:06
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    @HughFisher If we would only allow answers from the genuine designers of some device/machine, RC.SE would be some dead end. But it isn't, it's a 'market' of solution offerings. So add yours.
    – Raffzahn
    Oct 30, 2020 at 14:12

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