The 8080 does not know about any alignment. All access is byte access and linear. There is also no page logic. All addresses are handled as straight 16-bit and all data access is 8-bit.
(For additional musings see further down)
I assume it supports unaligned access, i.e. the address is not required to be even.
The 8080 does not handle or even know anything about alignment. A 16-bit value is simply stored at two consecutive (8 bit) memory locations.
Does it support fully unaligned access in all cases,
Yes, 16-bit load/stores can be done from any address.
no requirement that both bytes be in the same page?
No, the 8080 does not have a concept of 'pages'. All address pointers are 16-bit and increments are handled as such.
For example, if you try to write a 16-bit register pair to address $7fff, will the second byte be written to $8000?
Or if the stack pointer was set to $8001 and you perform a subroutine call, will the return address be written to the addresses $8000 and $7fff?
The 8080 as 16 Bit CPU
Yes, in some sense the 8080 (and its offspring 8085 and Z80) are 16-bit CPUs - at least when it comes to the register set and address handling. The register file is organized as
- a set of six 16-bit registers: BC, DE, HL, SP, IP and WZ (*2)
- directly connected to a 16-bit incrementer/decrementer
- directly connected to a 16-bit address latch
- which in turn is connected to the address bus.
Thus each of these registers can, within a single machine cycle be
- latched to be put on the (external) address bus, and/or
- incremented or
Note that there is no restriction by implied 'pages' or need for even/odd alignment, as address generation is plain 16 bit with a byte sized memory interface.
The 8080's internal structure is, regarding registers and addressing, fully 16-bit, whereas the 6502 is 8-bit in this respect, operating with separate 8-bit units to handle pages and addresses within pages. This pure 8-bit orientation of the 6502 made it lower cost, but added a few quirks, like dead cycles in case of 8 bit carry in (some) address calculations.
The question may stem from a mix-up between data size requirements and data bus size. Alignment issues can only come up with designs that have a finer address granularity than the external data bus and accessing a data item sized of multiple address units, i.e. a CPU with byte addressing but a multiple byte wide data bus accessing data wider than a single byte - like a 68020 (byte addressing, 4 byte wide data bus) accessing a 16 bit word.
The 8080 does not fall into this category. Addressable data unit and access width do not differ.
*1 - Or more correct it will be address 7FFFh and 8000h :)) SCNR
*2 - Note that AF is not one of them: A is a separate register, while F doesn't exist.