The 6502 had special support for BCD arithmetic, because it was widely used in those days; this much, it had in common with other CPUs.

But the 8080 and 6800 implemented this in the form of a 'decimal adjust after addition' instruction, the idea being that to add two pairs of BCD digits, you first of all add the bytes using the ordinary binary add instruction, which also sets half and full carry flags from four and eight bits respectively, then DAA checks the results and the flags and performs a fixup to make them correct for a BCD add.

Yet the 6502, designed by some of the inventors of the 6800, takes a different strategy; it provides a BCD mode, as a global flag which when set, causes all addition and subtraction to give the correct results for BCD until cleared.

This seems intuitively like a 'higher level' design, one that does more work for the programmer in order to more closely match intuition. That is particularly surprising because generally speaking the 6502 was a simpler processor that skimped on programmer comfort for the sake of lower cost.

Why did the 6502 designers choose this way of handling BCD? Was there some lesson learned after the 6800, some reason they figured this was the right way to do it after all?

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    Interesting question, I was recently thinking about posting a similar one. I don't know, but I imagine that the 6502 way is simpler to implement. Less state to preserve between addition and adjustment. But then you've got a horrible mode flag to save and restore when you're doing your interrupts and ting. Commented Nov 9, 2020 at 21:27
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    Another possibility, given the sparseness of the 6502's opcode map, would have been to fully decode the ROR and INC logic so that they'd only trigger on opcodes 011xxx10 and 111xxx10, respectively, and then use opcode bit 0 as a "BCD mode" flag. Alternatively, if all read-modify-write opcodes were fully decoded in such fashion, it would have been possible to shuffle around opcodes so that ORA/AND/EOR/CMP would have patterns 11smmms1 [where ss selects among those instructions] while 0scmmmd1 would be add or subtract (chosen by s), with c controlling carry suppression, and d controlling bcd.
    – supercat
    Commented Nov 9, 2020 at 21:44
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    @OmarL Seems to me you have exactly the same amount of state? The accumulator and carry flag exist in both kinds of CPU, so it's a choice between the half carry flag and the decimal mode flag, i.e. one extra bit of state either way.
    – rwallace
    Commented Nov 9, 2020 at 21:52
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    @rwallace: I have a strong suspicion that decisions about what instructions should be included were made before decisions about encoding. There's so much empty space in the opcode map that there would have been room to have many more instructions with eight addressing modes, which could have eliminated the need to have specialized logic to have instructions that only support a subset of addressing modes. Of course, the fact that people were able to make chips and have them work at all in 1976 given the tools that existed is pretty impressive in any case.
    – supercat
    Commented Nov 9, 2020 at 23:18
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    @rwallace: Still, without in any way faulting the designers of the 6502, I wonder whether a 6502-ish chip where all opcodes whose bottom two bits weren't both clear were processed using the same eight addressing modes controlled by the next eight addressing bits (using the same logic for all of them), except that read-modify-write or store-immediate would be replaced with branches, would have required more or less silicon than the actual design where many instructions support only a subset of addressing modes?
    – supercat
    Commented Nov 9, 2020 at 23:27

1 Answer 1


From the patent, "Integrated circuit microprocessor with parallel binary adder having on-the-fly correction to provide decimal results" (US3991307A) by Peddle et al. in 1975:

It is desirable in microprocessors to improve the speed by reducing the number of cycles necessary to perform a given operation. However, it is also desirable to have a minimum number of components, and it is typically not justified to have both a binary and a decimal adder in the same microprocessor. The prior art has typically chosen the disadvantage of using two cycles to get a decimal sum or difference rather than to suffer the cost of a separate decimal adder.

This invention takes a new approach to the problem: it uses only a binary adder to get the decimal sum or difference of two numbers, but does it in a single cycle of the binary adder, thus significantly improving the speed of operation without suffering the cost of an additional decimal adder. In accordance with the invention, the binary sum of two bcd operands is corrected by suitable gating as it travels from the binary adder to another part of the microprocessors, e.g., the accumulator, so that it becomes the binary coded decimal sum or difference of the two operands by the time it reaches that other part of the microprocessor.

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    Aha, thanks! So that explains why they moved on from the approach of using a separate adjustment instruction, though I am still curious why a status flag rather than a separate 'add decimal' instruction.
    – rwallace
    Commented Nov 9, 2020 at 22:02
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    @Chromatix: The opcode space on the 6502 isn't particularly "limited". Because there are no opcodes at all of the form xxxxxx11, it would have been simple to specify that all opcodes of that form will behave as an add or subtract, using bits 2-4 to select the addressing mode, bit 5 to select carry suppression, bit 6 to select decimal mode, and bit 7 to select addition or subtraction. Doing that would have freed up opcodes x11xxx01 to place two more eight-addressing-mode instructions.
    – supercat
    Commented Nov 11, 2020 at 0:01
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    Unfortunately, the architecture was chosen to justify a patent and thereby protect the design, but did not have any real technical merit. The adder circuit ended up being the critical path in the processor, which made the 6502 slower than e.g. a z80 running at their maximum rated speed. In general, a 1MHz (typical at the time) 6502 is half as fast as a 4MHz z80 (again, typical use). A classic example of legal considerations impairing performance for all users.
    – d3jones
    Commented Nov 11, 2020 at 0:17
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    Kevin, you should probably elaborate on why this would be important or desirable in the processor. That will also keep the answer from having no content besides copypasta + cite. Commented Nov 11, 2020 at 4:03
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    @rwallace No, it's just that they have more clock cycles per instruction, during which the ALU is available for use. The smaller ALU is also necessary to keep costs down with the Z80's overall more complex design.
    – Chromatix
    Commented Nov 11, 2020 at 7:16

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