The most controversial part of the IEEE 754 floating-point standard is gradual denormals. Typically they trap to software rather than being implemented in hardware. In the common case where a workload has numbers that decline to zero, when they hit the denormal range, there is an abrupt slowdown of a couple of orders of magnitude until the programmer finds out what's going on and how to turn off denormals. There is a good reason for this: in a nutshell, to make them run fast, would require spending more hardware resources all the time so that, for a given budget of transistors and power, everything would run slower in throughput, latency or both: https://stackoverflow.com/questions/54937154/why-are-denormal-floating-point-values-slower-to-handle
When the IEEE 754 committee was debating the matter, DEC hired an expert numerical analyst named Pete Stewart to study it and give his opinion, expecting him to support their position (based on experience with the VAX) that denormals should not be in the standard; they were unpleasantly surprised when he claimed they could in fact be implemented efficiently: https://people.eecs.berkeley.edu/~wkahan/19July10.pdf
But I haven't been able to find any specifics on how he expected this to be done. Presumably if the method he was thinking of would really work with no downside, modern CPUs would use it.
So what was he thinking? Why doesn't it work with no downside? Why did he believe it would? Was he ignoring latency and power consumption? Was he ignoring diffuse cost? (Sure, you can make denormals just as fast as normals – by making everything slower.) Was he working on assumptions that were true only with the technology of the time? (Gate delays exceeding wire delays, floating point implemented in microcode?) Or something else I haven't thought of?