The 8080 starts running code at location 0 on reset. The natural layout of memory on a computer using that CPU is therefore ROM at the bottom of the memory map and RAM at the top.

CP/M demands the reverse; it insists that ROM shall be at the top. The rationale is that this allows RAM to be used 'up until when it bumps into the ROM, wherever that happens to be' i.e. the entire address space can be filled with usable RAM right up until it bumps into the ROM that is actually installed in the machine, instead of having to set aside the first X kilobytes for ROM even if not all was actually used. This requires a small amount of extra circuitry to redirect the CPU from bottom to top of the address space on reset.

CP/M originated on the Altair 8800, an 8080-based machine.

But the Altair was a streamlined, indeed downright bare-bones machine, designed to minimize cost to be affordable to hobbyists in 1975. I would not have expected it to start off with the extra circuitry to redirect the CPU on reset.

When and how did the Altair acquire that extra circuitry necessary to accommodate CP/M?

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    I don't think that CP/M demands it. Boot rom can be active in memory at restart time, and then swapped out for ram when the boot loader is finished. The CP/M machine I used did that, and had a full 64 KB RAM memory Nov 12, 2020 at 13:42
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    Actually requiring RAM from zero address was a wise decision, at least for an OS (that is able to run arbitrary programs) for i8080 (that completely lacked PC-relative addressing). Other options would include the requirement for every program to be relocatable (=waste of resources) or some 'standard' ROM size at address 0 (which would exhaust soon and then again another ROM at higher addresses).
    – lvd
    Nov 12, 2020 at 17:20
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    @lvd: How much would it have cost to make a 8080 program relocatable on 256-byte boundaries? I would think that for most programs, all one would need would be to include at the start or end of the program (depending upon whether it loads at the top or bottom of RAM) a list of the offsets of all of the bytes whose value would be affected by the start address, and a loop (given as Z80 mnemonics) ld e,(hl) / inc hl / ld a,(hl) / add a,c / ld d,a / inc hl / ld a,(de) / add a,c / ld (de),a / jp nc,lp [the first address patched should be the jp instruction, and the last should be a dummy FF byte]
    – supercat
    Nov 12, 2020 at 18:37
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    "CP/M originated on the Altair 8800, an 8080-based machine." Are you absolutely sure about that? CP/M originated on whatever Kildall used for early development, and since he was contracting for Intel it was likely to be one of their ISIS development systems or similar. Nov 12, 2020 at 19:40
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    @supercat so in other words, a quite big list of offsets.
    – user253751
    Nov 13, 2020 at 16:58

1 Answer 1


It didn't move anything. There is no ROM at the beginning of memory. As the system did not include any code in ROM at all by default, ROMs were optional and usually placed at the end of memory. ROM is not needed, because the front panel can be used to halt the CPU, enter a program into RAM without CPU intervention, and command the CPU to execute the code loaded from front panel.

So if there is a ROM installed, user must operate the front panel to make the CPU execute commands at the address where ROM is installed.

In a system with no ROM at all, user must operate the front panel to load in the code to RAM and to execute it.

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    It might be worth more explicitly mentioning that while some other "trainer" computers use a monitor program in ROM to operate a front-panel interface, the Altair front panel switches can be used to place data in RAM without any CPU involvement whatsoever.
    – supercat
    Nov 12, 2020 at 16:19
  • @supercat This is not correct for the Altair. Unlike some other designs, the 8800 front panel ran the CPU to execute its functions. See e.g. the Theory of Operation Manual p.6 where it explains how pressing the examine switch starts CPU execution as the panel puts a JMP followed by the switch-set address on the bus and then halts the processor. (The data bus values for the post-JMP instruction fetch are displayed on the data LEDs.)
    – cjs
    Nov 8, 2021 at 14:54
  • If you think about it, any front panel that can set the program counter (or any other CPU register) on most microprocessors would have to run the CPU itself to do this since there's no external access to registers. Front panels that directly set memory instead of using the CPU (such as the Altair 680) had to restart CPU execution at the location of the previous stop or at the reset address.
    – cjs
    Nov 8, 2021 at 14:58
  • @cjs: Hmm... did the Altair use any kind of ROM chip, or did it just use hardwired arrangement of gates to form all of the necessary instructions?
    – supercat
    Nov 8, 2021 at 20:08
  • @supercat That's described on the exact page I gave you. "When the Examine switch is depressed the counter (IC J) is started. On the first count, a jump instruction (JMP 303) is strobed directly onto the bi-directional data bus at the processor. This is accomplished by enabling 2 gates of IC 2 and 2 gates of IC D through the output pin 6 of one gate of IC T. These open collector gates then pull down data lines D2, D3, D4 and D5. This puts 303 on the data bus, which is the code for a JMP." The schematic is also in that directory.
    – cjs
    Nov 9, 2021 at 11:21

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