How does this work from the endian-ness perspective?
Endianness is for most parts a software issue. Hardware, especially memory is either agnostic to the way a word ist stored, or doesn't have any idea about units wider than a byte at all(*1). Basically all I/O on S100 is 8 bit wide - after all, continuing the use of existing peripherals was a main point of continued use of the outdated S100 bus. Ther might have been a few, very special interfaces using the 16 bit wide data bus (*2), but there it depends on each individual card. S100 does not define a byte order.
In all practical situation endian issues will only arise if two S100 boards, with CPUs using different word endianes, share the same memory and data is exchanged/shared between them. Which is exactly the same as comes with every storage from RAM to floppy and punch tape to SSD, isn't it? So it's up to Software to handle this, not hardware.
but while the above link mentions several challenges, it doesn't mention that as one of them.
As the page is about hardware, not software.
*1 - Storing whatever comes along is the what RAM does, isn't it?
*2 - Maybe refer to this answer about S100 definition and extension to 16 bit.