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I am trying to understand the trade-offs between scalar and vector machines, the threshold of complexity/transistor count/performance at which vector machines started to make sense.

As data points, the Cray-1 was a vector machine, but the earlier CDC 6600 was not, and as far as I can tell, the CDC 7600 was not either.

So, defining a vector supercomputer as a machine on which you can add or multiply two vectors of floating-point numbers with a single instruction, and stipulating that each vector must be at least as large as two double precision numbers,

What was the first vector supercomputer?

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There are two computers meeting your definition: the CDC STAR 100 and the TI ASC, available in 1974. Both of these are memory-based vector computers, capable of issuing vector operations on data stored in memory, and storing the results in memory. The STAR could operate on vectors of up to 65,535 elements. Both systems could operate on double-precision floating-point numbers.

The first register-based vector supercomputer was the Cray 1, which also introduced chained operations; both of these improvements were largely a result of the difficulties encountered on the STAR and ASC — it was very difficult to reach anything like the nominal performance on both systems.

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    Nice, I wasn’t aware of that one! Does it qualify as a supercomputer? I’m guessing it doesn’t meet the “double-precision” requirement, does it? There was also the ILLIAC IV, but that’s really a massively-parallel computer, not a vector computer... Nov 17, 2020 at 17:16
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    :)) If I had considered it a valid answer,even remotely, I'd have written an answer. I just felt a nerdy urge to add it as distraction:) The Dietz 600 is a really neat CPU. Quite simple and powerful at the same time. As a microprocessor it might have bee THE one for early multi user systems. It was BTW as well sold by French Télémécanique as T621
    – Raffzahn
    Nov 17, 2020 at 18:20
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    @Raffzahn, I for one appreciate comments like yours that are not strictly on topic but does provide interesting information. Nov 18, 2020 at 6:44
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    @Lars agreed, and Retrocomputing.SE is somewhat unusual in the SE galaxy in this regard — in many cases there’s as much interesting information in the comments as in the answers! Nov 18, 2020 at 7:12
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    @StephenKitt It sometimes feels as if most RC.SE people are acting more like a team than lone wolfs. It's not about making one's answer 'the right one' than gathering of information and piercing history together. More we than in other SE areas. Not all harmony but mostly respect. Maybe because we got a good number of oldtimers who have experienced more than how to set the right braces around "Hello Word". ---- Just guessing.
    – Raffzahn
    Nov 18, 2020 at 22:18
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Another candidate, designed from 1972, prototype building started in 1974 was the ICL Distributed Array Processor (DAP) with a 64 * 64 bit SIMD architecture. First was shipped in 1979, (or perhaps 1978) and Edinburgh University had one around the same time (1980ish).

As I understand it, its 4096 Processing Elements (PEs) were 1-bit each, arranged as a 64x64 2-D array, so it could emulate 64 vectors each of 64 bits.

It was operated as a coprocessor to the ICL2900-series mainframes.

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