One thing to note – the 8088 registers are made from dynamic memory cells – they have to be refreshed.
This was unexpected (at least to me),
Same to me. And I guess to anyone else as well. Ken Shirriff's analysis of the 8086 registers clearly shows that they are not dynamic, but static, using the same inverter loop as the 8080 already did (and essentially every CPU of that time in one way or anotehr). The dynamic nature comes from different design elements - especially precharged busses, a very basic measure to speed up NMOS designs (see in part this answer).
It could end here, but it might be interesting to go thru the valid assumptions based from that quote:
It means you cannot freeze the CPU, but the only microcomputer I know of on which that is a feature/requirement is the Altair 8800 and clones (which were based on the 8080 and Z80).
They are not freezing the CPU, but simply taking over the bus, like in any other multi master system. The CPU is still clocked and running, but waiting on a bus access.
The 8088 was transitional to the 16-bit era. Presumably the earlier, 8-bit CPUs would have had even more need to conserve chip area.
True. But then again, there is less to save as well.
(Next to) Every saving comes with a cost to implement that. In case of dynamic RAM this is payed by the read out amplifiers, write back logic and refresh timing/cycles. So even if the CPU is made in a way that refresh can be done without spending clock cycles, the circuitry needed for reading/writing/refreshing is way more complex than a single or a few static cells. For dynamic RAM it pays, as here hundrets of rows share the same read/write/refresh logic. In a 16 KiBit RAM (4016) 128 bits (one from each row) share the same logic. That gives savings allowing sbstantial investment and still save over all.
Even a register rich CPU as the 8080 does have only six registers that can be (and are) handled as a group like a RAM (BC, DE, HL, WZ, PC, SP). Not much dough to form the additional circuitry.
In addition it's worth to remember that registers on an 8080 are not formed as full figured RAM cells, but simply as two inverters hooked up as a loop - that's two transistors. Writing them is done by forcing a vaue in from a 'stronger' source. Replacing such a cell them by a dynamic one might not save anything at all, as that requires at least one transistor and a capacitor - the later eventually bigger than a single transistor.
Did any of the 8-bit CPUs use dynamic memory cells for registers?
Not that I know of. The often cited dynamic behaviour of the NMOS 6502 is not due the registers itself, but the way intermediate values are handled on the busses.
If not, why not?
As shown, there is for one not much to save from, but the kind of register cells used are already pretty tiny. Even with the 8086 and its 15 register there is not enough savings - ignoring for a moment the implication of steady refresh on a CPU design).
Do static cells run faster, did designers expect people to want to be able to freeze the CPU, or is there some other disadvantage?
Not really. Static are (over all) faster, but that wouldn't matter as CPUs not even use full figured static cells. It's important to keep in mind that while a register can be seen as a memory cell from a logic PoV, they are not, or often not, when implemented the same way than memory - Register design has different constrains.
And holding a CPU steady on a per clock base (I guess that's what your "freezing" is supposed to mean) is done in different ways, depending on CPU type/structure.
Long story short: While some CPU may have used classic static memory arrays for registers - and some even dynamic - most didn't, especially not early on and when different design may give advantages.