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According to https://jamiestarling.com/project-8088-the-8088-cpu-pinout/

One thing to note – the 8088 registers are made from dynamic memory cells – they have to be refreshed. The minimum clock speed for any 8088 is 2Mhz. The max depends on the chip you are using.

This was unexpected (at least to me), though logical from the viewpoint of saving chip area; dynamic memory cells are smaller than static ones. It means you cannot freeze the CPU, but the only microcomputer I know of on which that is a feature/requirement is the Altair 8800 and clones (which were based on the 8080 and Z80).

The 8088 was transitional to the 16-bit era. Presumably the earlier, 8-bit CPUs would have had even more need to conserve chip area.

Did any of the 8-bit CPUs use dynamic memory cells for registers? If not, why not? Do static cells run faster, did designers expect people to want to be able to freeze the CPU, or is there some other disadvantage?

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    This isn’t an answer to your question, but some 8-bit CPUs effectively used a part of RAM as registers (e.g. page 0 on the 6502). – Stephen Kitt Nov 19 '20 at 13:58
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    @StephenKitt Not to mention TI's TMS9900 (16 Bit), were the whole workspace (Registerset) was in RAM :) Or many /360 models were the user visible register set was stored in a dedicated RAM area. – Raffzahn Nov 19 '20 at 15:54
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    ISTR, back in the day, microprocessors that specified no minimum clock frequency were the exception rather than the rule. – Solomon Slow Nov 19 '20 at 17:34
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One thing to note – the 8088 registers are made from dynamic memory cells – they have to be refreshed.

This was unexpected (at least to me),

Same to me. And I guess to anyone else as well. Ken Shirriff's analysis of the 8086 registers clearly shows that they are not dynamic, but static, using the same inverter loop as the 8080 already did (and essentially every CPU of that time in one way or anotehr). The dynamic nature comes from different design elements - especially precharged busses, a very basic measure to speed up NMOS designs (see in part this answer).


It could end here, but it might be interesting to go thru the valid assumptions based from that quote:

It means you cannot freeze the CPU, but the only microcomputer I know of on which that is a feature/requirement is the Altair 8800 and clones (which were based on the 8080 and Z80).

They are not freezing the CPU, but simply taking over the bus, like in any other multi master system. The CPU is still clocked and running, but waiting on a bus access.

The 8088 was transitional to the 16-bit era. Presumably the earlier, 8-bit CPUs would have had even more need to conserve chip area.

True. But then again, there is less to save as well.

(Next to) Every saving comes with a cost to implement that. In case of dynamic RAM this is payed by the read out amplifiers, write back logic and refresh timing/cycles. So even if the CPU is made in a way that refresh can be done without spending clock cycles, the circuitry needed for reading/writing/refreshing is way more complex than a single or a few static cells. For dynamic RAM it pays, as here hundrets of rows share the same read/write/refresh logic. In a 16 KiBit RAM (4016) 128 bits (one from each row) share the same logic. That gives savings allowing sbstantial investment and still save over all.

Even a register rich CPU as the 8080 does have only six registers that can be (and are) handled as a group like a RAM (BC, DE, HL, WZ, PC, SP). Not much dough to form the additional circuitry.

In addition it's worth to remember that registers on an 8080 are not formed as full figured RAM cells, but simply as two inverters hooked up as a loop - that's two transistors. Writing them is done by forcing a vaue in from a 'stronger' source. Replacing such a cell them by a dynamic one might not save anything at all, as that requires at least one transistor and a capacitor - the later eventually bigger than a single transistor.

Did any of the 8-bit CPUs use dynamic memory cells for registers?

Not that I know of. The often cited dynamic behaviour of the NMOS 6502 is not due the registers itself, but the way intermediate values are handled on the busses.

If not, why not?

As shown, there is for one not much to save from, but the kind of register cells used are already pretty tiny. Even with the 8086 and its 15 register there is not enough savings - ignoring for a moment the implication of steady refresh on a CPU design).

Do static cells run faster, did designers expect people to want to be able to freeze the CPU, or is there some other disadvantage?

Not really. Static are (over all) faster, but that wouldn't matter as CPUs not even use full figured static cells. It's important to keep in mind that while a register can be seen as a memory cell from a logic PoV, they are not, or often not, when implemented the same way than memory - Register design has different constrains.

And holding a CPU steady on a per clock base (I guess that's what your "freezing" is supposed to mean) is done in different ways, depending on CPU type/structure.

Long story short: While some CPU may have used classic static memory arrays for registers - and some even dynamic - most didn't, especially not early on and when different design may give advantages.

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    The term "register" is often used not just to refer to program-addressable registers, but more generally to circuits used to hold temporary values. As such, I think the buses of the 6502 could be thought of as registers. – supercat Nov 19 '20 at 18:56
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    Also, there are a number of forms of "dynamic" memory. An minimal NMOS static latching circuit requires an active transistor to control writing, an active transistor and passive pull-up to read out the value, and one active transistor and one passive pull-up to hold the value. Eliminating the "holding" transistor and associated pull-up would yield a dynamic latch, which would only hold the value for a limited time, but wouldn't require any extra circuitry. – supercat Nov 19 '20 at 21:14
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It is my understanding that many microprocessors used dynamic logic. The likes of the 6800,6809 and the 6502 used this.

This reference discusses one such technique: https://en.m.wikipedia.org/wiki/Four-phase_logic

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  • Yes, but the processors you mention don't use RAM for registers. – Chenmunka Nov 22 '20 at 12:44
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    The question was ‘dynamic memory’. A register is considered a storage device thus ‘memory’. If the registers were implemented relying on the gate charge of a mosfet, that would satisfy the criteria of dynamic memory. – Kartman Nov 23 '20 at 20:10

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