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On the Apple II series of computers, peripheral cards contend for bus mastership through a priority daisy-chain system. A peripheral card is only allowed to perform DMA if its DMA_IN line is at logic 1, indicating that no higher-priority cards are using the bus. When performing DMA, a card must set DMA_OUT to logic "0" in order to inhibit lower-priority cards from mastering the bus.

However, I have recently become aware of a different convention regarding the DMA_IN and DMA_OUT lines. Some ROM cards and Language Card-type RAM cards use the DMA_IN and DMA_OUT lines to arbitrate between multiple cards using the /INH feature. This can be seen in the Apple 050-0009-01 ROM card schematic, in which the DMA_OUT line is a logical AND between DMA_IN and the enable signal for the onboard ROMs.

I can understand this usage of the DMA_IN and DMA_OUT lines, but where can I see this usage of the DMA priority daisy chain discussed further?

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    Only a comment as I do not have a link like asked for. Since the logic is as well tied to the ROM address range and reading, it's not really about DMS, but using the same line to disable have 'downstream' cards. It was intended to allow the use of an Applesoft Card (ROM Card) in slot 0 and a Language Card in slot 1 Later this was as well needed for RAM cards using the Language Card's scheme for larger memory expansion. In some sense it's a hack to allow two of such cards to coexist. This worked especially since real DMA was not only rare,but usually writing as well. – Raffzahn Dec 8 '20 at 12:34
  • Marginally related is this question - most important here the statement about DMA cards being notoriously picky when not being the only on in the system. – Raffzahn Dec 8 '20 at 12:49
  • @Raffzahn: Out of curiosity, could DMA request be used to drive ready for a precision CPU stall, or did cards provide another means of asserting READY, or would the Apple's hardware have required that a device drive the address bus and control signals when asserting DMA request? I would think that some kinds of data acquisition could be made much easier if a load could be delayed until data was ready. For example, if a high-density floppy controller could stall the CPU until data was ready, it could avoid the need to use the MSB of each byte as... – supercat Dec 8 '20 at 17:08
  • ...a data-ready signal, and also avoid the need to branch until ready and deal with the resulting timing uncertainties. If it only stalled the CPU while the drive motor was on, and software "turned off" the drive motor before reading, the drive motor turning off would allow the CPU to become "unstuck" if no data arrives. – supercat Dec 8 '20 at 17:11
  • @supercat That is simply what RDY is for. Pulling DMA as well would for one turn the Address drivers off, resulting in no address seen from the load, but any higher priority DMA could still interfere. The Apple II bus isn't very well designed in terms of multi mastering. I guess that would be a lot to ask from a rather quick design focused on cost cutting. – Raffzahn Dec 8 '20 at 17:52

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