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Dynamic RAM is denser than static RAM, but needs to be refreshed every few milliseconds to avoid losing data. How many milliseconds, exactly? If the answer has changed over time, then I'm interested in what it was on the RAM chips used in the seventies and eighties.

What prompted the question was that I was under the impression some computers used the video circuitry to do the refresh, which would suggest it sufficed to do it once per 60 Hz frame, which would be about 16 ms, but according to http://www.jagregory.com/abrash-black-book/

Each DRAM chip in the PC must be completely refreshed about once every four milliseconds in order to ensure the integrity of the data it stores.

Was 4 ms the typical figure for standard DRAM chips?

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    You could check the datasheets. The TMS4116, for instance. has a 2 ms refresh interval (pdf.datasheetcatalog.com/datasheets/700/237022_DS.pdf). Also, note that "using the video circuitry to do the refresh" does not automatically imply "doing one refresh per frame". It depends on which bits of the address are used for the row, and which for the column. – Michael Graf Jan 18 at 9:24
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    As mentioned below in an answer, IBM PC 5150 uses about 66.3kHz timer rate to refresh 128 rows of memory in 1.93ms. IBM VGA does 3 refresh cycles per line in the blanking area, with a line rate of 31.47kHz to refresh 256 rows in 2.71ms. – Justme Jan 18 at 19:21
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Was 4 ms the typical figure for standard DRAM chips?

Only starting with 128kbit and 256kbit chips. Many earlier chips (16kbit, 32kbit, 64kbit) and some 128kbit chips were documented as requiring a 2 ms refresh cycle; see these tables for details: 4116, 4132, 4164, 41128, 41256.

The fact that many computers used the video circuitry to handle DRAM refresh doesn’t mean that that refresh happened at the same rate as the video refresh. See What is DRAM refresh and why is the weird Apple II video memory layout affected by it? for a description of the Apple II’s implementation. In the 8-bit Ataris, DRAM refresh was handled by ANTIC, with a dedicated counter for that purpose; see the Atari 8-bit FAQ for details. Reenigne wrote a blog post explaining DRAM refresh on the IBM 5150 (not using the video circuitry).

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About that video thing: Early chips have a 7bit refresh, so you have to access all rows in a 2ms frame. You could swap some address lines to achieve more (physical) rows access per cycle.

In an extreme case, you can swap A0-A6 and A7-A13 completely, so for linear access will be each byte stored in a totally different physical row. Et voila, you have a "free refresh" by design (and a lot of headaches, because it is very slow). So it is possible, but it needs some kind of trade-off.

See also: Why do Early DRAMs (e.g. 4116) have a negative Column Address Set-up Time?

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