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Modern out of order CPUs can do all sorts of things in parallel, having not only multiple functional units, but a lot of logic to check at runtime exactly which instructions really depend on others, so as to extract as much instruction level parallelism as possible.

The first microprocessors, of course, were strictly serial devices, which would finish one instruction before beginning the next. Even when pipelining was introduced, e.g. with early RISC CPUs like MIPS and ARM, each instruction would both start after, and end after, the previous one.

It seems to me that after pipelining, the next step in instruction level parallelism would be to try to do other things while waiting on a memory access. Once clock speeds get into double-digit megahertz, main memory is expected to be slow relative to the CPU (cache helps, but the hit rate is never 100%), and if you could start a load going, then do something else for a couple of cycles until it finishes, you could gain instruction level parallelism without needing multiple functional units.

What was the first microprocessor that could do ALU operations (independent of the value being loaded, e.g. in other registers) while a load from memory was in progress?

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    To clarify: The 6502 was microprogrammed, so do microprogrammed CPUs that fetch the instruction register in parallel with doing other work count? I guess there'd be quite a few of those earlier than the 6502. Also, keep in mind that if we are talking 6502 or earlier, memory is usually faster than the CPU, so if you want parallelism, you want that on the CPU.
    – dirkt
    Jan 18, 2021 at 10:00
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    @dirkt: I wouldn't really call the 6502 microprogrammed. It does use a PLA internally, but the term "microprogrammed" usually refers to CPUs whose microcode can branch and loop; the 6502, by contrast, advances through states purely in sequence except when it skips to the start of the next instruction, or when it the main sequencer is stalled either because the "ready" signal is low or the CPU is performing a read-modify-write sequence (which is controlled via a different latch).
    – supercat
    Jan 18, 2021 at 17:41
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    Why only "microprocessors"? For this I think we have to go back to at least the CDC 6600.
    – another-dave
    Jan 18, 2021 at 23:43
  • If one excludes delayed loads such as used by MIPS R2000 (where the load operation has a fixed delay during which another independent operation could execute), this ability is called "non-blocking loads". In-order designs which use a scoreboard to determine operation readiness could support such (and load operations are one of the common multicycle and variable latency operations).
    – Paul A. Clayton
    Feb 19, 2021 at 16:19

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I suspect this isn’t quite the answer you’re looking for, but there’s no need to wait for RISC...

What was the first microprocessor that could do ALU operations (independent of the value being loaded, e.g. in other registers) while a load from memory was in progress?

I think the answer is the 6502, which fetches the next instruction before the current instruction has finished executing.

This type of pipelining ended up being common, with various designs. The 8088/8086 has a separate bus interface and execution unit, and the former prefetches instructions while the latter is busy executing instructions.

The answer to your clarifying comment,

what I'm asking for is not the first pipelined microprocessor but the first one to go beyond that and allow 'start a data load from memory, then do something else, then finish the data load and do something with the loaded data'.

which I’m interpreting as, the first microprocessor which would be capable of handling a sequence of instructions involving a memory load followed by an independent operation, by starting the memory load, setting that instruction aside, handling the following operation, and coming back to the memory load — which is effectively instruction reordering — is the first microprocessor to implement instruction reordering, which I think was the PowerPC 601 in 1993. It can emit instructions to its branch-processing unit, its integer unit, and its FPU in parallel, and handle their results in whatever order they arrive; it can also reorder memory loads and stores. Memory loads are handled in the IU, and are considered complete once the address translation is done, so the IU can go on to other things before the load completes.

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  • Right, I remembered the 8088 does instruction prefetch, forgot the 6502 does some degree of it also; these are forms of pipelining, for a reasonably inclusive definition of the term. But what I'm asking for is not the first pipelined microprocessor but the first one to go beyond that and allow 'start a data load from memory, then do something else, then finish the data load and do something with the loaded data'.
    – rwallace
    Jan 18, 2021 at 9:49
  • When using a read operation with absolute indexed or zero-page indexed addressing, the 6502 also overlaps the LSB address computation with the MSB address load, which allows it to save a cycle in cases where the MSB address can be used verbatim.
    – supercat
    Jan 18, 2021 at 15:29
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    Yes. While @rwallace mentions doing other things while waiting for memory load, historically it was the other way around since ALU instructions can sometimes take multiple clock cycles and clocks were designed to run at memory speed. So historically parallelism started with loading from memory while waiting for a math instruction to complete
    – slebetman
    Jan 19, 2021 at 7:36
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The Motorola 68882, while not strictly a microprocessor but a coprocessor, was explicitly designed to handle loads and format conversions in parallel with arithmetic operations. This was, in fact, the main advantage it held over its immediate predecessor, the 68881. The 68882 was available by at least 1988, as the Macintosh IIx included it.

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If you consider the 68030 and 68882 combination as a single CPU, then the following sequence of operations was possible:

1: The 68882 is instructed to begin an arithmetic operation. Some such operations (eg. taking the logarithm) could take hundreds of cycles to complete.

2: The 68882 is instructed to load a single-precision operand for a subsequent calculation. This takes a number of cycles in the 68882's CU to convert it to 80-bit internal format. The load and conversion proceeds independently of the arithmetic operation already in progress in the AU.

3: Once the load portion of item 2 is complete, the 68030 then loads and executes operations on integer and address operands while both the AU and CU in the 68882 are busy.

4: The 68882 is then instructed to perform arithmetic on the operand just loaded. This must wait for the conversion to complete (making the operand available in the register file) and for the previous arithmetic operation to complete (making the AU available). However, the 68882 can buffer the instruction and allow the 68030 to proceed with further instructions, provided it doesn't need to load any data.

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