The device I'm using (a SYM-1, probably c. 1979) has a stack of L2114-UCE 1024x4 static RAM chips ("2114 static, TTL in/out 1024x4 N-MOS RAM", the -UCE means "450ns access time, 315mW max. power dissipation").

They get hot enough that they're just about at the "ow, that's really hot!" point. Are there compatible replacements for these chips that would produce less heat output?

  • 4
    What's your concern? Is it the electricity usage or the temperature? If the latter, you may be able to add heatsinks. If the former, is it significant compared to other components? Commented Feb 3, 2021 at 16:51
  • @TobySpeight Great point.
    – Raffzahn
    Commented Feb 3, 2021 at 18:26
  • Do you just want something that has compatible timing and voltage levels, or do you want a direct 'plug in' replacement for each chip? Commented Feb 4, 2021 at 19:48
  • A direct plug-in replacement would be awesome, but reading through the answers it sounds like I'm more likely to find something electrically compatible but not physically compatible. That's fine; I'm mostly thinking about how to deal with failures in 40 year old tech :).
    – larsks
    Commented Feb 4, 2021 at 20:41

3 Answers 3


Sure, like using a single 6264. These are usually CMOS, so with a (for nowadays) low clock rate as with the SYM they shouldn't produce much heat. It is a 64 KiBit chip, so the whole 8 KiB comes in one package. For all usage, it's as similar to the ones used as possible. In fact, some can live from a few µA, so buffering is a possibility.

Finding pin-compatible replacements will be a bit harder, as for these small sizes x4 versions aren't common anymore.

Also, I'm not really sure why one would want to replace them, except for increasing size (like with a 32 KiB 62256 type). Their temperature might seem high by today's standard, but I bet it's still way within spec. Getting hot is what NMOS does :). The relationship between computing power and power consumption was simply more visible, wasn't it?


Just about any "modern" 8-bit SRAM chip can be used to substitute for these, with the understanding that the pinout will be different and you'll need fewer of them. There are inexpensive 2Kx8 devices which will substitute nicely for up to four 1Kx4 originals, and 8Kx8 devices that will substitute for as many as sixteen.

In general this will also obviate the need for some decoding circuitry. In the SYM-1 specifically, there's a 74LS138 interposed between the 3-NOR gate detecting the bottom 8K of address space, and the four pairs of 2114 SRAM sockets; the four lower outputs of the '138 drive /CS of one pair of sockets each, while the others appear to lead only to the expansion connector. A single 6264 SRAM (8Kx8) could replace both the 74LS138 and the eight socketed 2114, to provide twice the usable RAM of the standard configuration. It should be straightforward to build a one or two-layer PCB daughtercard which plugs into the original sockets to obtain all the necessary signal lines to lead them to a 6264.

Any surplus address or data lines can be tied high or low - directly for address lines, through a 1K resistor for data. The original devices do not have /OE pins, so these can simply be tied to the /CE or /CS pins (same function, just different possible names) on the replacements. If there is an active-high CE2 (as on the 6264), tie it high.

Power consumption on modern CMOS SRAM devices is negligible, compared to the rest of a predominantly NMOS/LSTTL based system.

  • Just be careful with "too modern" - SRAM chips meant for caches on 486/586 PCs can be 3.3v only, and can be much too fast for the board layout - something with 7ns access time will be on the level of 74AC logic when it comes to demands regarding signal integrity because not only the access speed but the output rise times will be much faster, and so will be the sensitivity to ringing and the potential to create prodigous amount of EMI. If you ever breadboarded with 74AC or ECL parts, you will know actual clock speeds do not matter when it comes to signal integrity... Commented Jan 24, 2023 at 0:08

A typical NMOS SRAM chip can be viewed as having two buckets for each bit, both of which have water slowly flowing into them, and either of which, when appreciably filled, will opens the drain of the other (draining a bucket will close the other bucket's drain). Writing a bit is accomplished by holding the drain on one of the buckets open long enough that its contents will drain, the other bucket's valve will close, and that other bucket will fill enough to open the valve on the first one. Once that has happened, the bucket that had been drained will remain empty because its valve is open, while the other bucket will remain full (keeping the former bucket's drain open) because its own valve is closed and any water that might leak out will be constantly replenished.

The designers of a chip could reduce the amount of power it consumes continuously by reducing the rate at which water constantly flows into the buckets, but that would increase the length of time required to write a bit. Instead, many chips are designed to let a substantial amount of water flow through the buckets, so as to increase the rate at which a bucket will fill after its partner is drained.

While the amount of heat generated by such chips may seem abnormal by today's standards, the chips run hot because the designers were willing to accept a high amount of energy waste in order to maximize performance. Unless one has a need to minimize energy usage or heat generation, one should simply recognize that the devices were designed to run hot as a normal operating condition.

  • This is only true for certain SRAM designs.
    – Raffzahn
    Commented Feb 3, 2021 at 20:02
  • @Raffzahn: I said "a typical NMOS SRAM". Certainly it would not be true of a typical CMOS SRAM. Have there been any NMOS devices that built memory cells that didn't use a pair feedback transistors with passive pullups?
    – supercat
    Commented Feb 3, 2021 at 20:18
  • 1
    There are many variants - like for example middle tap 6T which reduces power by 40-70%. The world is quite colourful, isn't it?
    – Raffzahn
    Commented Feb 3, 2021 at 20:24
  • @Raffzahn: Not familiar with that design. Got any links? How common were different NMOS SRAM designs, and did that change with time? Would my statement be more accurate if I said "a typical 1970s-era NMOS SRAM"?
    – supercat
    Commented Feb 3, 2021 at 20:28
  • @Raffzahn: When I tried searching for NMOS SRAM, I mostly seemed to get links to CMOS memory designs. Does "middle tap 6T" simply use an intermediate ("middle tap?") voltage for the passive pull-ups within the array than for e.g. the pull-ups driving the row gates, or what makes it special? And do you know if the design of the 2114 differed substantially from what I was describing? I know I simplified the passive fill design, since in reality the passive pull-ups would only have enough pressure to push water into the empty bucket rather than the full one, but do you see any other issues?
    – supercat
    Commented Feb 4, 2021 at 17:20

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