According to https://en.wikipedia.org/wiki/Data_General_Nova

The Nova 1200 executed core memory access instructions (LDA and STA) in 2.55 microseconds (μs). Use of read-only memory saved 0.4 μs. Accumulator instructions (ADD, SUB, COM, NEG, etc.) took 1.55 μs, MUL 2.55 μs, DIV 3.75 μs, ISZ 3.15-4.5 μs.

Okay, many of those instruction times look reasonable and unsurprising...

... Wait a minute. Integer division in 3.75 microseconds? On a machine that took 1.55 microseconds for addition? How?! I understand you can make multiply fast if you are prepared to spend logic gates on a Wallace tree multiplier, but how could division possibly be made that fast? Even decades later, on chips that could easily throw millions of transistors at doing steps in parallel, divide was the one instruction that remained much slower than regular ALU operations. How did the Nova make it that fast in the 1970s?

  • 6
    Pretty sure it's just a typo or misreading. The manual for the Nova 800 (the faster sibling) gives DIV as 8.8 µs but vaguely specifies "unsuccessful 1.6 µs" as well. Maybe it means 1.6 µs to object to a divide by zero? 1.6 µs is the basic cycle time for the 800. That manual is on Bitsavers.
    – RETRAC
    Feb 5, 2021 at 6:51
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    @RETRAC "Unsuccessful division" is also immediately flagged when the upper 16 bits of the dividend are no less than the divisor, i.e. when the quotient will overflow.
    – Leo B.
    Feb 5, 2021 at 7:03
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    @RETRAC A document which lists the basic instruction latency as 1.55 μs instead of 1.6 μs would likely list the DIV latency as 8.75 μs, and misreading it as 3.75 is plausible. But still, given that 8.8 / 1.6 = 5.5, it appears that dual phase clocking was used, and even given a reasonably-sized lookup table I wonder how they have achieved 5.5*2 = 11 pipeline stages.
    – Leo B.
    Feb 5, 2021 at 7:19
  • 3
    I guess it’s also possible that the machine had long cycle times that sandbagged the speed of addition. Division and addition are equally fast, if one cycle is long enough to divide.
    – Davislor
    Feb 5, 2021 at 7:29
  • 2
    I used to use the DG1200. Don't remember a MUL or DIV instruction but it doesn't mean they weren't there The low level stuff that was mainly done in assembler was just moving data about. It was always in nice multiples of 2 so a MUL or DIV was never required.
    – cup
    Feb 5, 2021 at 9:21

1 Answer 1


Not a complete answer, but a bit of information from the manual (for several Novas including the 1200):

The hardware multiply-divide option for the Nova is actually a peripheral device connected to the in-out bus, although it has no flags or interrupt capability. It contains A, B and C registers, which are loaded and read by the standard IO transfer instructions, and which correspond in use respectively to accumulators 0, 1 and 2 with respect to the multiply and divide software routines and the processor hardware option in the other computers. [...]

Following the IO instruction that starts the multiply or divide, the program must wait until the result is available in the A and B registers. Multiplication takes 6.4 μs, division takes either 6.8 or 7.2 μs depending on the operands. Of course the program can do something useful with the time (such as loading an accumulator for the next operation), but usually one simply gives a couple of no-ops to pass the time.

That suggests that the division hardware is completely independent from the main CPU, does not use the ALU of the main CPU, and can use a clock as fast as the specialized hardware allows.

According to Wikipedia, the Nova 1200 used a single 4-bit ALU. If they used multiple 4-bit ALUs in the multiplication/division hardware, and if you take into consideration that accumulator instructions have delays from other operations on top of using the single ALU four times to arrive at the 1.55 μs total, then the timing for division starts to fit.

(To see how it actually worked, one would have to find documentation for the multiply-divide option, but I couldn't find any).

  • 1
    The difference of 0.4 μs between 7.2 and 6.8 suggests that the clock period of the device is at most 0.4 μs, therefore 6.8 μs (a multiple of 17 cycles) is plenty to produce 16 bits of the quotient. The extra clock cycle was needed to correct the result when the final subtraction produced a negative remainder, see wiki
    – Leo B.
    Feb 5, 2021 at 9:45
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    @LeoB except that those devices not necessarily use a central clock for timing. The Nova 800/1200 CPU actually does; the PDP-8 doesn't, and they may have squeezed out a few μs out of the mul-div option by not using a central clock with uniform cycles. As I wrote, one would need to see the schematics...
    – dirkt
    Feb 5, 2021 at 11:46
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    Another thing to note is that an iterative multiply or divide algorithm may be able to exploit carry-save addition or subtraction, thus allowing a clock period to be shorter than the time required to perform a "normal" addition or subtraction.
    – supercat
    Feb 5, 2021 at 18:29

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