Three are ICs labeled memory select used in Apple II.

One to apply A6 on the three banks of RAM ICs.

One to generate /RAM_SEL applying the latched RAM output to the data bus.

And one to apply /CAS on the three banks of RAM ICs.

On the schematics they appear like this:

enter image description here

On the board like that:

enter image description here

I need to know the logic of this IC: What are the three inputs from one side, the 7 inputs from another side and how they define the three outputs.


2 Answers 2


I need to know the logic of this IC:

They are not IC, but bridges (wires) connecting the inputs to the chips, depending what type is plugged in each of the RAM rows.

What are the three inputs from one side, the 7 inputs from another side

It's marked on the schematics, isn't it?

They are fed by the decoded address signals from the 139's left of the excerpt, which in turn get their input from the 257 multiplexers, which in turn get fed by the A12..A15 from CPU or Video.

Output is A6 (for 16 Ki) and CAS (Pin 13/15 of the RAMs), as well as RAMSEL used to multiplex the data in lines. All right of the excerpt.

Nothing spectacular, just wiring.

and how they define the three outputs.

By connecting whatever is needed for the desired combination.

What exists:

Originally there were 4 different types:

  • For 1..3 rows of 4 Ki RAMs marked 4K/4K/4K
  • For one row of 16 Ki and 0..2 Rows of 4 Ki RAMs marked 16K/4K/4K
  • For one or two Rows of 16 Ki or two rows of 16 Ki and one row of 4 Ki RAMs marked 16K/16K/4K
  • For 1..3 rows of 16 Ki RAMs marked 16K/16K/16K

The later is is the most common and fixed in place on the later runs of early boards - like seen in the picture.


It's a single solution to two problems

  1. 4 Ki and 16 Ki RAM chips have a differing pinout and voltages
  2. The plugs allow the creation of a continuous address space without needing dedicated decoders for each row.

What Configurations are Possible?

  • 8/8/12 KiB with 4K/4K/4K plugs
  • 16/20/24 KiB with 16K/4K/4K plugs
  • 16/32/36 KiB with 16K/16K/4K plugs
  • 16/32/48 KiB with 16K/16K/16K plugs
  • I see, thank you. But I still need to know the interconnection for 16K RAMs to implement Apple II on FPGA. I will try to find it out myself. "4 Ki and 16 Ki RAM chips have a differing pinout and voltages" helped me to understand why we need it. Feb 7, 2021 at 20:49
  • 1
    @PaulGhobril Come on, it's just CAS and RAM A6 - which is naturally CPU A12/A13 in 16Ki configuration - I think it's safe to assume that you're not doing any configuration with less than 48 KiB. Since you're doing an FPGA, the RAM part will work different anyway. No multiplexing of addresses, no CAS/RAS timing and so on.
    – Raffzahn
    Feb 7, 2021 at 22:03
  • Indeed, but just to get the whole picture. Feb 7, 2021 at 22:06
  • @PaulGhobril BTW, if you're doing the memory system, it might be a good idea to allocate some shadow memory for the text/graphics pages ($400..BFF, $4000..$7FFF) to decouple parallel read access of video and CPU. CPU writing to both, while video only reading from shadow memory. Most FPGA offer independent Read and Write to (some) RAM, which, used as shadow memory, makes all video generation complete timing independent, easing the connection of modern output quite a lot - not to mention the ability to speed-up/Slow down the CPU part at will without interfering with video.
    – Raffzahn
    Feb 7, 2021 at 22:16
  • Thank you for these suggestions. In fact I have already implemented a C64 nine years ago on Altera (Intel now) and now I am fascinated by how Apple II did all VIC and CIAs functionalities by common TTL ICs and to be honest at first sight I thought that these "Memory select" are equivalent to PLA in C64 but now it is clear. Feb 7, 2021 at 22:26

It's almost certainly not an IC but just a passive set of wire links that are routed differently depending the memory configuration.

You may be able to work out what is needed from the signals available on the left and what is required on the right.

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