I need to know the logic of this IC:
They are not IC, but bridges (wires) connecting the inputs to the chips, depending what type is plugged in each of the RAM rows.
What are the three inputs from one side, the 7 inputs from another side
It's marked on the schematics, isn't it?
They are fed by the decoded address signals from the 139's left of the excerpt, which in turn get their input from the 257 multiplexers, which in turn get fed by the A12..A15 from CPU or Video.
Output is A6 (for 16 Ki) and CAS (Pin 13/15 of the RAMs), as well as RAMSEL used to multiplex the data in lines. All right of the excerpt.
Nothing spectacular, just wiring.
and how they define the three outputs.
By connecting whatever is needed for the desired combination.
Originally there were 4 different types:
- For 1..3 rows of 4 Ki RAMs marked 4K/4K/4K
- For one row of 16 Ki and 0..2 Rows of 4 Ki RAMs marked 16K/4K/4K
- For one or two Rows of 16 Ki or two rows of 16 Ki and one row of 4 Ki RAMs marked 16K/16K/4K
- For 1..3 rows of 16 Ki RAMs marked 16K/16K/16K
The later is is the most common and fixed in place on the later runs of early boards - like seen in the picture.
It's a single solution to two problems
- 4 Ki and 16 Ki RAM chips have a differing pinout and voltages
- The plugs allow the creation of a continuous address space without needing dedicated decoders for each row.
What Configurations are Possible?
- 8/8/12 KiB with 4K/4K/4K plugs
- 16/20/24 KiB with 16K/4K/4K plugs
- 16/32/36 KiB with 16K/16K/4K plugs
- 16/32/48 KiB with 16K/16K/16K plugs