Following my previous question on Identifying the functionality of the memory select in Apple II and now that I know that the memory select device is simply an interconnection block. Searching for more, I found the Apple II red book where the memory select is explained with the following figure:

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So I represent the interconnection scheme as I got it. For 16K/16K/16k:

enter image description here

For 16K/4K/4K:

enter image description here

Now the question is: why the last 4K block is (6000 - EFFF) and not (8000 - 8FFF)?

Is it related to RAM mirroring, bank-switched ROM or anything else?

  • It probably is a typo. However, it is worth noting that BASIC in the Apple 1 needed RAM in the $E000-$EFFF address range. – DrSheldon Feb 12 at 13:01
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    @DrSheldon it seems it is a typo but check this: retrocomputing.stackexchange.com/a/6020/18338 – Paul Ghobril Feb 12 at 13:07
  • To clarify my comment: It's plausible that while Woz was developing the Apple II, he used the BASIC from the Apple 1. That would require having RAM in the $E000-$EFFF address range. Once the II had its own BASIC, such a mapping would no longer be necessary. It would also explain why there were jumpers for address ranges that were apparently never used. – DrSheldon Feb 12 at 15:16
  • @DrSheldon thank you it is clear now. I misunderstood your first comment. – Paul Ghobril Feb 12 at 16:08

Actually my book has $8000-$8FFF for pin 7 (but it's a German translation).

And it's also $8000-$8FFF in the Apple II Reference manual on archive.org, p. 71.

And it's also $8000-$8FFF in the Apple II red book on archive.org, p. 133, though you can see that there is a hand-drawn correction in it.

So, a mistake that was later corrected? Can you give a link to the Apple II red book where you found it?


I'm not near my Red Book at the moment, but a quick look at the schematics seems to support (*1) your assumption of Block 7 being $8000-$8FFF.

The fine details of how it's decoded are rather complex. You may want to take a look at how thee 139's on position E2/F2 are connected to the address lines (A12..15), and especially how E2 is enabled, as well as note that what is A6 on a 16 Ki RAM (4116) is /CS on a 4 Ki type (4096).

*1 - Haven't drawn up the full table, so no guarantee here.

  • What advantage would there be with having a decode for 0x8000-0x8FFF rather than selecting the top 4K bank for all addresses 0x8000-0xBFFF? Even if one wanted to use an expansion board to push beyond 36K, I would think a bank of 16K DRAM chips would be cheaper than an expansion board that used 4K DRAM chips. – supercat Feb 8 at 19:53
  • @supercat Keep in mind, the design for the Apple II was made at a time when 4 Ki Chips were available and 16 Ki only announced recently. Also, what you want can simply be done by using the 16/16/16 block for CAS. But that would be a hack, disabling ecpansion for that area on interface cards. – Raffzahn Feb 8 at 22:37
  • My question was why Apple bothered generating that chip select, when omitting it would have made the circuitry simpler (looking at the schematic, I think there are a couple of gates whose purpose is to tweak the inputs to a 74LS139 so it yields the proper output, though I don't quite understand how the circuit is supposed to work). Using a 74LS138 to yield eight consecutive outputs and just using the first six would seem like it would have been simpler. – supercat Feb 8 at 23:26
  • @supercat Keep in mind, it handles video access as well, the decoding comes almost for free. I not really sure that Woz can be accused of wasting gates, or would you think so? – Raffzahn Feb 8 at 23:28
  • Woz was brilliant, but that doesn't mean his design was perfect. If there was a need to have a decode for the exact region $8000-$9FFF, his circuit is probably a good way of getting that, but the circuit could have been simpler if pins 7-8 had simply been connected on the motherboard in the places that generate CAS for 4K DRAM chips, but pin 7 was connected to pins 1-6 where those are all tied together. – supercat Feb 8 at 23:39

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