Why does the 6502 read from the stack before writing it?

Question

I am building a W65C02S based computer for fun, and I try to build basically all the tools myself. Including the assembler (yes, I know they exist, I just want to make everything from scratch myself, for fun).

When working on the JSR opcode (absolute addressing mode), I find that before it puts the program counter on the stack, it reads one byte off the stack first (program counter is set to 80 2e at this point, the stack pointer is 01b6):

READ  address:   80 2e   data:   20   JSR   ; Read the opcode
READ  address:   80 2f   data:   14   14    ; Read the LO byte of operand
READ  address:   01 b6   data:   74   't'   ; Read the stack (why?!)
WRITE address:   01 b6   data:   80   ---   ; Write HI byte of PC
WRITE address:   01 b5   data:   30   '0'   ; Write LO byte of PC
READ  address:   80 30   data:   80   80    ; Read HI byte of operand
READ  address:   80 14   data:   8d   STA   ; Read opcode at `80 14` (the JSR operand)

It works OK, but what it the reason it reads from the stack first?

(To explain the table: this is from my own tool. I am using an Arduino to look at the data and address buses to see what is happening there. It is a hardware CPU running only my own code.)

Answer 1

[This question is kind of duplicate to

• 6502 double store and copy protection?
• What is the MOS 6502 doing on each cycle of an instruction?]

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TL;DR:

It's one of the 'dead' or internal cycles of a 6500. On a WDC65C02 they are externally all turned into 'harmless' read cycles.

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Background

Unlike other CPUs the 6500 series has not pure internal cycles without memory access, but each and every cycle will as well be a memory cycle. Whenever internal operation can not overlap with with a needed memory cycle, a dummy access is inserted. Usually with the last address used.

• On NMOS it depends on what the next (intended) cycle would be, read or write.

• On CMOS this was changed that the internal cycle would always be a read.

This behaviour will be as well seen on RMW instructions and all inserted carry processing cycles on page crossings.

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The Finer Details

The detailed working are described on page 107 of the 1976 MCS6500 Microcomputer Family Programming Manual:

Notable here is that cycle 3 stores the just read ADL, the low byte of the target address, which then gets overwritten in cycle 4 by PCL. This is of course like the NMOS version works.

As mentioned, when the CMOS version was designed one goal was to remove all unintended write operations (*1). In this case the third cycle writing ADL was replaced by a dummy read.

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P.S.: If you're starting from scratch, it might be a good start to first read both 1976 manuals end to end :)

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*1 - While it doesn't really matter when looking at RAM, unintended writes may screw the workings of I/O ports. The 6500 being mainly meant as an embedded CPU family this counts an important improvement.