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This answer to the question "What was the rationale behind 36 bit computer architectures?" makes the point that early computers were assembled by hand, rather than having central processing units on one chip. The number of CPU bits were chosen carefully to fulfill the needs of the architecture, rather than necessarily choosing a power of 2. To that end, what was the last central processing unit made commercially available that was not on one chip?


Clarification: To avoid this degenerating into an "anything goes" question, the following functions do not count, even if they occur outside the CPU:

  • Power regulation, reset conditioning, and clock generation do not count, because it could apply to nearly every computer (except some microcontrollers).

  • "CPU" implies arithmetic, logic, and control. It specifically does not include memory, nor the interface to memory. Therefore ROM, RAM, bus demultiplexers, bus buffers/transceivers, address decoding, caches, memory management units, northbridges, and mass storage do not count because they are part of the memory system.

  • Similarly, "CPU" does not include input or output. Thus peripherals and southbridges do not count because they are part of I/O.

  • Floating-point units and other co-processors do not count, as the CPU could still execute basic programs without them. Notably, co-processors were available and often used with early x86 and 68k processors, yet the CPU was still functional without them.

  • Using multiple chips to include multiple processors is not the scope of the question.

  • Any CPU that markets itself as a microprocessor or microcontroller is probably against the spirit of this question, as the intention of a microprocessor is to put the entire CPU on one chip.

As there is already one good answer, the question is certainly answerable.

Because the question is asking for the "last" instance, please include the year that the CPU came to market in your answer.


Related: Was there ever a genuine "mainframe-on-a-chip" microprocessor?

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    Re, "...necessarily choosing a power of two" That probably has a lot to do with the fact that the people who design CPUs are not the same as the people who design computer systems around those CPUs, and not the same as the people who design the memory system components. If you want a wider memory bus that what's available from COTS memory modules, then it's easy to double-up on the next smaller size. Hence, powers of 2, all the way down. – Solomon Slow Feb 25 at 19:03
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    The question is quite misleading and I can't get what the asker really meant. For example, 'cache' is said to be an 'add-on' -- quite an understatement as L1 caches are the essence of any decent fast CPU! Same with MMU (MMU and L1 caches are working together in tight coupling in any decent CPU). Same with 'co-processors' which now became the CPU itself (that is, FPU and vector parts of the CPU). And then even amd ryzen would fit author's definition -- it is NOT a single-chip design and separate core silicon chip itself won't work without another IO silicon chip. – lvd Feb 25 at 19:59
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    Putting this as a comment because its not what you're looking for but there is at least one true multi-chip microprocessor, the Fairchild F8. A minimum functional CPU requires two chips, one ALU (3850), and one with instruction decoding and a 1KB ROM (3851). A 3rd chip (either 3852 for DRAM or 3853 for static RAM) is required if you need to address more than the onboard 64 bytes of RAM though, with an optional 4th chip (3854) for DMA. – mnem Feb 26 at 4:04
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    @mnem: Yes, you are correct that it both meets the requirements of the question, but also that it was not the last. – DrSheldon Feb 26 at 4:12
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    @lvd while the L1 cache is a key part of modern CPUs (outside of very low cost/power embedded) but earlier designs didn't use it. eg the 486 was the first x86 CPU with onboard cache; it was an external option for 286/386 systems but ram of the era was fast enough relative to the CPU that memory performance wasn't a major performance bottleneck like today. retrocomputing.stackexchange.com/questions/11247/… – Dan Is Fiddling By Firelight Feb 26 at 19:43
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The world of large computers is amazing. MCM systems of monstrous in the eyes of a PC user parameters were widely popular right up to the cloud revolution, and even now, taking into account legal restrictions, they are actively used in banks.

Just remember IBM POWER2+ in a six-chip configuration for one core (not counting L2 cache) (video) - it was launched on the market in May 1994.

PS

But the Japanese vector supercomputer monster, NEC SX-5, appeared even later!

In June 1998, SX-5, the fourth generation in this series, was unveiled. Doubling both the clock frequency and the number of vector pipelines, the evolved model achieved CPU vector per- formance of 8GFLOPS, system peak vector performance of 4TFLOPS with a configuration of parallel processing with 512 CPUs.

The release of the fifth generation SX-6 in October 2001 in- troduced the integration of the previous model’s CPU of 30 LSIs in a single chip.(link)

Each CPU had a maximum performance of 8 gigaFLOPS, four times the maximum performance of the SX-4 series, by using high-density ultra-fast CMOS LSIs, built with cutting-edge 0.25-micron design rules, and 64 Mbit synchronized DRAM. (link)

CPU (intact with heatsink) photo.

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    Thanks for adding the link. If I'm reading it correctly, the FXU chip is where the integer ALU instructions are done, and the ICU chip is an instruction cache, but is also where instruction decoding and branches are done. So you got it +1, more than one chip was used for CPU functions. The multi-chip-module also had an FPU and other caches, which don't matter for this question. – DrSheldon Feb 26 at 3:55
  • Splitting responsibilities like that is surprisingly rational (to me). I was expecting these systems to be multi-chip purely because of monstrous size and arbitrarily divided, but having your instruction cache be responsible for working out what each means and where next is very sensible, as is keeping the cache separate for modularity. – Dan Sheppard Mar 5 at 9:16
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    @DanSheppard That is necessary with this approach. There are thousands of signals on chip, but only dozens to a couple hundred pins available for off-chip communication. The result is a modular and bus-oriented approach that can make optimal re-use of limited wires. Indeed, the approach has generally been maintained up to today, and is now just done on-die with busses connecting various parts of the IC together to minimize random traces running madly all over. – RETRAC Mar 18 at 20:50
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The last commercial non-integrated main processor introduction that I can recall was the one in Tandem NonStop Cyclone systems, introduced circa 1989. The CPU seems to have been 3 large printed circuit boards full of ECL gate arrays.

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  • Similar to my VAX 9000 answer. It looks like the two were near-contemporaries. – another-dave Feb 25 at 23:59
  • Interesting that this answer and another-dave's both involve emitter-coupled-logic. Which makes sense because it's fast (which is very marketable to some customers) but also there's too much power dissipation for one chip. – DrSheldon Feb 26 at 4:01
  • By 1989, the 68030, and other microprocessors of that vintage, were competitive with TTL discrete CPUs, but at a much lower cost. So there was no reason to not use a uP unless customers were willing to pay a lot more for more performance. Thus very big hot ECL designs. – hotpaw2 Feb 26 at 5:05
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The VAX 9000, first ship 1990, must be a contender here.

Per Wikipedia,

Each CPU was implemented with 13 Multi-Chip Units (MCUs), with each MCU containing several emitter-coupled logic (ECL) macrocell arrays which contained the CPU logic.

By the time it was released, the 9000's price/performance had been eclipsed by systems based on NVAX, a single-chip processor.

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  • Since the OP mentioned 36-bit architectures, I have to mention the transition from the DEC KI10 processor, based on logic, and the KL10, based on a Motorola 6800. The KI-10 was decades before the VAX9000, but marked the transition over to microprocessor based emulation in the KL-10. – Walter Mitty Feb 26 at 11:31
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    How'd you get a KL10 out of a 1MHz 8-bit microprocessor even with microcoding? I'll have to go read about it. My experience was all with the KI 10. – another-dave Feb 26 at 12:35
  • I'm hazy on the details. But I do recall that the KL-10 was based around a microprocessor, I believe a motorola 6800, that emulated the PDP-10 instruction set. It's a bit of a stretch to call a PDP-10 a mainframe, and a bit of a stretch to call tthe KL "monolithic". After all, it had a PDP-11 as a console front end. And the PDP-11 was capable of loading the microcode into the microprocessor. – Walter Mitty Feb 26 at 13:15
  • I need to correct myself. The KL did have microcode, but the microcode was fed into gates that controlled the CPU internal logic. I don't understand the explanation completely. I checked in with the DEC Alumni group over in Facebook, and they corrected me. – Walter Mitty Feb 27 at 11:09
  • Again, sorry about spreading misinformation. I programmed the DEC-10, but I never interacted directly with microcode. That was all at a layer below what was visible to me. – Walter Mitty Feb 27 at 11:12
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what was the last central processing unit made commercially available that was not on one chip?

The 8-bit discrete logic processor kit!

enter image description here

It is commercially available now (you can buy it from the website above).

It is multi-chip since it's made of 74LS chip.

And... it is definitely retro.

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It depends. Some CPUs needed specific support chips, e.g. Intel 8080 (1974) needed (cited from Wikipedia) "i8224 clock generator/driver and the i8228 bus controller". Indeed, one of the advantages of Z80 was no need for these additional chips.

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  • I had known about the 8224 when writing the question, which is why I said that microprocessors are not in the spirit of the question. And whatever happens to the address or data buses outside of the CPU is not part of the CPU itself. – DrSheldon Feb 25 at 19:03
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    There is NO need in 8224 or 8228 chips for 8080, meaning you can gеt away without them easily. Here is an example: spetsialist-mx.ru/schemes/Spetsialist.png . Clock phases are made with +12v pullups and open-collector drivers so that 8224 is not needed, dropping IO space and interrupts support means no need in 8228. – lvd Feb 25 at 19:51
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    The Intel iAPX 432, a microprocessor, required 2 chips to make up the CPU alone, there was a third chip that was almost always used/necessary. (I never saw a 432 system without it.) But it was terminated in 1986 which means there are later candidates in other answers anyway. – davidbak Feb 26 at 0:52
  • You can start here: github.com/PDP-10/microcode/commit/… – Walter Mitty Feb 26 at 13:19
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I believe the correct answer is the IBM Q System One.

It's a quantum computer which is currently offered for commercial use. Although I've never seen a specification of exactly what electronics it uses, I'm reasonably certain it uses more than one chip (I'm reasonably certain nobody has a clue of how to build such a CPU on a single chip at the present time).

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    It is not a CPU. – Leo B. Feb 26 at 7:56
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    It is not retrocomputing. – OmarL Feb 26 at 9:47
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    Yes, it is (or at least has) a CPU. @OmarL: If the correct answer to a question is off-topic, then the problem is that the question is off-topic. – Jerry Coffin Feb 26 at 17:08
  • @OmarL - it is not retrocomputing here, but a long time ago in a galaxy far far away ... – davidbak Feb 26 at 18:42
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Honeywell had a CPU that was 36-bit from 1970-1989 (which one might say was ahead of its time as IBM said that on their 32-bit machines years ago they needed one more bit because they only used 31-bits and used the high order bit to determine the end of a list of addresses as passed as parms)

The CPU operated on 36-bit words,[10] and addresses were 18 bits. The Accumulator Register (AQ) was 72 bits, or could be accessed separately as two 36-bit registers (A and Q) or four 18-bit registers (AU,AL,QU,QL). An eight-bit Exponent Register contained the exponent for floating point operations (the mantissa was in AQ). There were eight eighteen-bit index registers X0 through X7.[11]

The 18-bit Base Address Register (BAR) contained the base address and number of 1024-word blocks assigned to the program (the 6180 used segmentation rather than the BAR). The system also included several special-purpose registers: an 18-bit Instruction Counter (IC) and a 27-bit Timer Register (TR) with a resolution of 2 μs. Sets of special registers were used for fault detection and debugging.

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    Which question were you answering with that? – Leo B. Feb 26 at 1:03
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    This seems to perhaps answer another question that was linked in this question, but not this question itself. – DrSheldon Feb 26 at 1:12

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