This question occurred to me while I was formulating this answer about arithmetic versus logical shifts.
The IBM 709, and its descendant the 7090, etc., is a 36-bit mainframe with a classical single-accumulator architecture, word-addressed memory, and so on.
Unusually (or so it seems to me), the accumulator is slightly wider than the word size: it is 38 bits rather than 36 bits.
Where a memory word is considered to have a sign bit S and 35 magnitude bits (1-35, with 1 being the MSB), the accumulator has sign bit S, and bits Q, P, and 1-35, with Q and P being "to the left of" bit 1. Incidentally, this nomenclature shows the downside of adopting big-endian bit numbering.
The extra bits provide the benefit of explicitly retaining information that overflows from addition and subtraction operations. Neither bit P nor Q is "the" overflow indicator; the overflow is set as bits pass in or through P -- the temptation to look at this as just a odd way to regard condition codes does not seem to me to work out.
However, the extra two bits in the "middle" of the accumulator means that the instruction set distinguishes loading the AC with an arithmetic value from loading AC with a logical (unsigned) value. The former copies the memory word into S and 1-35, clearing P and Q. The latter copies it into P and 1-35, clearing S and Q.
Anyway, to get round to the question: apart from the 709 and its 7-series offspring, were there other systems that had registers "slightly larger" than memory words? Any non-IBM systems?
Here I use "registers" in the modern sense, as being logically a part of the CPU, and distinct from memory.
I want to exclude computers that support multiple operand lengths -- e.g., a 32-bit machine with 32-bit registers that also has 16-bit arithmetic, and computers with double-length registers for supporting (for example) full-word multiply with a double-length result.
It's the "couple of extra bits" aspect that intrigues me.
This paper on the design of the IBM 701 discusses the decisions leading to extending the accumulator by two bits (see p 1270).