NexGen was best known for the unique implementation of the x86 architecture in its processors. NexGen's CPUs were designed very differently from other processors based on the x86 instruction set at the time: the processor would translate code designed to run on the traditionally CISC-based x86 architecture to run on the chip's internal RISC architecture. The architecture was used in later AMD chips such as the K6, and to an extent most x86 processors today implement a "hybrid" architecture similar to those used in NexGen's processors (https://en.wikipedia.org/wiki/NexGen).
How does this “internal RISC architecture” work and why is it so successful to be widely used today? Did the concept originate from NexGen or was it already being used in other non-x86 CISC processors? Further was this NexGen’s main design goal, or just one of many?
Edit to give extra context around the answers. The P5 Pentium was the first superscalar x86 processor; the Nx586 , P6 Pentium Pro  and AMD K5 [1996, based on a 29k RISC processor with an x86 decoding front end] were among the first designs which decode x86-instructions asynchronously into dynamic microcode-like micro-op sequences prior to actual execution on a superscalar microarchitecture; this opened up for dynamic scheduling of buffered partial instructions and enabled more parallelism to be extracted compared to the more rigid methods used in the simpler P5 Pentium; it also simplified speculative execution and allowed higher clock frequencies compared to designs such as the advanced Cyrix 6x86. [Wikipedia Superscalar Processor]. Thus although the K6 (1997) was a different design created by NexGen engineers, AMD had already implemented an x86 processor with RISC-like internals in the K5.