The Intel 4004 had 4-bit buses and data words, but the program counter and code address space was 12 bits. Was the 4004 little endian (like all of Intel's later microprocessors and microcontrollers) or big endian?
You can find here the Intel 4004 datasheet.
You can see from the 4004 Instruction Set table on page 4 that the 3 nibbles of a jump target address (in ROM) are stored with the highest order nibble in the first byte of the instruction, and the two other nibbles in the 2nd byte. Thus we conclude that in the instruction set fields > 4 bits are stored with the highest bits in the lower address, thus big-endian.
As for the instructions themselves, the datasheet refers to the "upper 4 bits" and "lower 4 bits" of the 8-bit instruction (for the 1-word instructions). For consistency with the representation of addresses I think we can conclude that the "upper 4 bits" are at the lower address, thus instructions are stored in ROM big-endian as well.
Update: Here's a better argument: Looking now at the second byte of two byte instructions we see that the 2nd nibble of the address is stored in the "upper 4 bits" and the 3rd in the "lower 4 bits". If instruction bytes themselves were stored big-endian than the 3 nibbles of a ROM address are in order high-middle-low from low address to high. But if the instruction bytes are in little-endian order then the 3 nibbles are high-low-middle in memory address order - which would be weird. So we conclude that instruction byte are stored big-endian in ROM.
Other than that I don't believe "endianness" applies: As a 4-bit processor with 4-bit registers and data paths and no "double precision" instructions - there is no other appearance of "endianness" in the architecture.
(These are just my conclusions from wording on the datasheets. Someone who inspects an actual 4004 machine code dump, or a 4004 assembler, will have the definitive answer.)