The Intel 4004 had 4-bit buses and data words, but the program counter and code address space was 12 bits. Was the 4004 little endian (like all of Intel's later microprocessors and microcontrollers) or big endian?

  • The +50 answer here stackoverflow.com/questions/5185551/why-is-x86-little-endian gives slight indirect evidence that it was big endian since it explains why the 8008 went with little endian, in particular the quote by Stan Mazor who it says worked on the designs of the 4004 and 8008. – Single Malt Mar 7 at 21:56
  • @SingleMalt: Yes, I already knew that it was Datapoint -- not Intel -- who designed the 8008 architecture, and that its choice of little-endian was due to its use in a calculator. Which makes it all the more interesting that the 4004 was exactly the opposite. Little-endian architectures was not Intel's original choice; it was imposed upon them by Datapoint. – DrSheldon Mar 7 at 22:52

You can find here the Intel 4004 datasheet.

You can see from the 4004 Instruction Set table on page 4 that the 3 nibbles of a jump target address (in ROM) are stored with the highest order nibble in the first byte of the instruction, and the two other nibbles in the 2nd byte. Thus we conclude that in the instruction set fields > 4 bits are stored with the highest bits in the lower address, thus big-endian.

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As for the instructions themselves, the datasheet refers to the "upper 4 bits" and "lower 4 bits" of the 8-bit instruction (for the 1-word instructions). For consistency with the representation of addresses I think we can conclude that the "upper 4 bits" are at the lower address, thus instructions are stored in ROM big-endian as well.

Update: Here's a better argument: Looking now at the second byte of two byte instructions we see that the 2nd nibble of the address is stored in the "upper 4 bits" and the 3rd in the "lower 4 bits". If instruction bytes themselves were stored big-endian than the 3 nibbles of a ROM address are in order high-middle-low from low address to high. But if the instruction bytes are in little-endian order then the 3 nibbles are high-low-middle in memory address order - which would be weird. So we conclude that instruction byte are stored big-endian in ROM.

Other than that I don't believe "endianness" applies: As a 4-bit processor with 4-bit registers and data paths and no "double precision" instructions - there is no other appearance of "endianness" in the architecture.

(These are just my conclusions from wording on the datasheets. Someone who inspects an actual 4004 machine code dump, or a 4004 assembler, will have the definitive answer.)

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    Interestingly, the point where I expected the endianness to appear—function calls—does exist in 4004, but the call stack is more like the register stack akin to x87 st(n), not the now-usual stack in the RAM as the SP-driven one in x86. So no trace of endianness here too. – Ruslan Mar 7 at 18:18
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    I don't think it makes sense to refer to endianness in cases where some of the operand bits are mixed with opcode bits. Even if other aspects of the CPU were definitely little-endian, putting target-address bits 8-11 in the instruction and having the operand hold address 0-7 would allow every operational step that loads any of PC address bits 0-7 to load them all. By contrast, if the instruction byte held bits 0-3, then fetching the operand byte would require loading bits 0-7 when processing a conditional jump or 4-11 when processing an unconditional jump. – supercat Mar 7 at 19:13

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