Older CPUs have been shrunk to smaller sizes but not in the same way as modern design, simply as there is no gain in doing so.
Does the industry continue to produce outdated architecture CPUs with leading-edge process?
No. Designs shrink, but there is no sense in using leading-edge sizes for such 'small' designs.
However, is there any CPU produced in, say, 14 nm process, but with as few transistors as the original 8086 or 80386
No, as these designs simply have gate counts that are too small to make it worthwhile. A 386 has at least 132 pins, each needing a pad on the die to connect to. With actual bonding technology a pad needs about 100-150µm, so 132 pads will take some 16mm (rounded for simplicity), making the chip at least 4x4 mm in size - or more precisely, that'll be the inner size available to its circuitry. That's a full 16mm². Using 12nm process that's enough for more than 200-300 million transistors, but an 80386 has under 300 thousand. It'll fit in 1000 times. Heck, even throwing in a 387 as well wouldn't change it much. No need to take on all the disadvantages of small node size without any gain.
The Long Read
Scruss's answer about the greatly revamped 8051 isn't wrong - the 8051 ISA is still a major seller in micro controllers, not least due to quite mature tools being available for them. But at the same time, these new 8051's have about as much in common with the original Intel CPU as a i7 has in common with an 8086. Yes, it has a mode to run the same code, but everything else is as different as it can get. Like apples and oranges.
The same goes for all examples involving ARM. True, a Cortex something (ARMv7/8) can run most code from an ARM 6 (ARMv3), but its inner workings and structure are different in almost all aspects.
But there are several real old CPUs that are still in production today, using the same internal structure, only shrunk to a newer production process. Not least classics like Z80 and 6502, the later making a great example about usefulness of shrinking as well.
The original NMOS 6502 was produced in an 8 µm process and was later moved to 6 µm, while its WDC follow up, the 65C02 started out on a 3µm process (*1). Over the years the CPU was implemented using various processes, including 2µm, 1.5µm, 1.2µm, 0.8µm, 0.6µm, 0.5µm and 0.35µm. All of them used the same original design, adapted to new processes without being modified/extended otherwise. This includes of course embedded versions.
Unlike many other classic chips, the 65C02 is still available new in 2021 with exactly the same internal structure as it was in 1983. Now produced in 0.6 µm (600nm) by TSMC. Yes, the very same TSMC that astonishes with Ryzen CPUs in 7nm operates 'still' a 600nm production line - and it has a bright future.
It might seem strange that today's 65C02 is manufactured in 600nm when it has already been used with 350 nm, as mentioned above, but shrinking does not always make much sense. Sure, when it's about squeezing milliards of transistors into a space as small as possible, shrinking does help. But what if there are features that do not allow further shrinking? Like these stupid little pads a chip needs for bonding for example? A 6502 needs 40 pins connected, thus at least 40 pads around the outer rim, as seen here:
The image is taken from this nice video and features the 1993 800nm version. It shows that, already at that 'crude' size, the minimum area possible, defined by maximum packed pads, sufficient to hold the CPU is reached. Looking closely reveals a comparable large unused area between pads and their pull up/down circuits (*2) and the CPU circuitry. Any further process shrink will therefore not bring savings in area, but only add complications.
It is often forgotten that shrinking adds problems, often quite a lot. A large effort in today's processor design goes into minimizing or mitigating these effects. Heat is the most obvious, but usually not of concern for ancient designs with a few thousand gates. With shrinking size, elements get more sensible for all kinds of distortion, foremost voltage. It is not only for power saving that modern CPUs operate at ridiculously low voltages (like the mentioned 7nm Ryzen with 1.1 to 1.4 Volt): the fine structures would simply fry at higher voltage.
Related to that, shrinking voltage and node size causes parasitic loss to increase. So if low power is a major goal, the smallest available structure size is not a good choice.
Not to mention that rough environments (Military use, Space, etc.) love to kill fine structures on sight, so having bigger ones is a measure of safety.
But There is an Area Where Older CPUs do Shrink Further
The picture changes a bit when not only looking at the CPU itself, but it being a part of a system that gets shrunk together. Imagine a system consisting of
- Z80 CPU,
- Z80 DMA,
- Z80 PIO (maybe more than one)
- Z80 SIO (")
- 2 KiB of Boot-ROM
- 32 KiB of FLASH
- 2..32 KiB of RAM
To be shrunk into a System on a Chip (SoC). Here each of these additional components is in terms of space requirement comparable, if not higher than the CPU itself. Especially the RAM/FLASH part. Together they come out easy as 20-30 times the CPU alone. Since reduction goes by square, a 25 times larger amount of components will need to be shrunk by 5 to give the same area.
So while it does not make any sense to shrink a 6502 or Z80 below 5-600 nm feature size, a SoC based on such does make sense in 100..120 nm technology, but not below. That is of course only if it doesn't need more pins - as their number is again the limiting factor.
*1 - Being CMOS this was in part compensated by needing about 2.5 times as many gates.
*2 - It nicely shows the difference between power pins, which simply connect to ground and power layer, and signal pins with their drivers. Seeing the drivers already orientated radially (inside and outside of the pads) show that the chip is already optimized for size. In comparison, the original NMOS 6502 (warning, extremely large image) was so large that there was enough space between the pads for many of the drivers to be moved there.