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With the ubiquity of FPGAs, I find it relatively easy to design an eighties-like CPU. But it's maybe too simple now, with so many ways to implement any given CPU unit.

What were the hardware constraints that the designers back then had to contend with?

How were units like the register file, the ALU or the microcode actually implemented? For example, how many ports did the designers use for the register file, did they use simple ripple-carry adders in the ALU or more complex ones, etc.

Was there something like LUT already? Were there some original designs that differed significantly from others?

Is there some reference material available online? I'm especially interested in the 6502, Z80, 6809, 8086, 68000 and 80386.

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    Except for the 80386 those were all designed and released in the 1970's.
    – Brian
    Mar 23 at 12:41
  • @Brian: yes, I know that. But I didn't say that they were designed in the 80s, just that they were popular at that time. Indeed, almost every home computer of the era were based on those few chips. I added the 386 because it's of special interest to me, as it marks the limit between the 80s and the 90s (in my view, anyway).
    – airman
    Mar 23 at 13:04
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    There's some pretty good information on how the Z80 was laid out (laboriously, by hand) to be cleaned from an interview featuring Federico Faggin, Masatoshi Shima and Ralph Ungermann. Mar 23 at 13:10
  • It doesn’t answer your question because it wasn’t feasible for CPUs but in case you’re curious about the tangent, look into PALs and ULAs for the ‘80s forerunners of FPGAs. A ULA is a bunch of standard prefabricated slabs of transistors to which a connecting mesh is added just-in-time to produce a custom chip. Electronic design tools were often used. So it’s a bit like an FPGA without the F and with the P being achieved by the addition of a final custom physical layer.
    – Tommy
    Mar 23 at 16:28
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    On @Tommy s note, particular users of ULAs in computers were Acorn Computers (BBC Micro series) and Sinclair (ZX81, ZX Spectrum, QL). They'll show you what the 'buyer-customised' gate arrays of those days were capable of. Far tinier circuits than FPGAs. Btw, FPGAs use up far more transistors to be configurable than are needed to produce the equivalent circuit in an ASIC, so very few gates would be possible if they made one back then. And they wouldn't have today's dirt-cheap Flash EPROM to configure their tiny FPGA from, just fairly expensive EPROM in bulky packages. But that's for an answer.
    – TonyM
    Mar 24 at 20:14
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In those days, there were few if any computer-aided design tools. IC design work was done by hand, up to and including the preparation of photolithography masks using a scalpel and a steady hand. These were then photo-duplicated at a reduced size for application to the actual manufacturing process.

In the 1970s, the main technologies suitable for building microprocessors were LSTTL (using bipolar transistors) and NMOS (using resistors and field-effect transistors). The 6502 benefited from what was then a very new innovation in NMOS by MOS Technology, using depletion-mode transistors as the high-side biasing element instead of resistors, which saved a lot of die space and improved efficiency; this was improved further by the use of "dynamic logic" in which the biasing element and the pull-down transistors that actually implement the logic are not switched on at the same time, but only in alternate halves of the clock cycle. This technology was not available to the first versions of the 8080 or 6800, which were its main contemporaries. It may have been used in the 8086 and the 68000.

The 6502 was overall a major exercise in cost-performance optimisation, with the objective of reducing the transistor count and (particularly) die size to a point where the yield was high enough to permit a low sales price, yet still with a profit margin. For this purpose, about 5000 transistors was considered the limit, about half that of the 6800, and many times less than the 68000. There is no room in such a budget for niceties like a carry-lookahead adder, and a clever (patented) trick was needed to even squeeze in the Decimal mode of the ALU.

Instead of a large microcode ROM containing a separate row for each opcode, a series of smaller ROMs was used to divide each instruction's function into distinct, independent parts. ADC instructions with different addressing modes, therefore, would all decode to the ADC row in the ALU microcode ROM, but different rows of the addressing mode microcode ROM. This both saved die space and reduced the chances for errors in microprogramming. It also resulted in the 6502 having a comparatively orthogonal instruction set for its class (certainly when compared to the Z80 or 8086), making it easier to code for.

You can explore all the gory details at Visual 6502.

In the 1980s, there was a definite shift towards the more power-efficient CMOS technology, which had previously been very slow. It was found that reducing the thickness of the gate oxide in the individual NMOS and PMOS transistors sped them up a lot, at the expense of the maximum voltage they could tolerate. Since older CMOS could tolerate over 12 volts, a reduction to 5 volts was no problem and allowed easier interoperability between CMOS and existing LSTTL/NMOS logic. Most of the popular NMOS CPU families gained CMOS versions, often gaining more functionality in the process since the logic had to be completely redrawn in any case.

CPUs as complex as the 68030 were still hand-drawn for lithography, the blueprints being laid out in large rooms with engineers literally crawling over them to work. There was some movement towards using computers to assist the design process in the mid-1980s; for example Acorn used their existing BBC Micros to simulate various aspects of their new ARM CPU, to verify their correctness and ensure the proposed instruction set was actually usable. This resulted in the first ARM1 prototype arriving from the foundry and working first time - which was virtually unprecedented in CPU design history. The industry took notice of that.

Incidentally, the ARM1 also still used a ripple-carry adder, which was still sufficient to do a 32-bit addition in one cycle at a modest clock speed. Something more sophisticated was implemented for the ARM2, which also added a hardware multiply instruction.

One technique used then, but which is no longer viable today, is the installation of a small-scale chip fabricator in the design offices of some manufacturers. This allowed prototype chips and individual microcircuit experiments to be carried out without interrupting the mass production lines at the main fab. It was extensively used by Commodore after they bought MOS, including specifically for the design of the VIC-II and SID.

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  • sorry, I forgot to replace "designed" by "implemented" in my first edit. Although the design process is fascinating, I'm more curious about tricks of the trade that were used when creating specific units of a given CPU.
    – airman
    Mar 23 at 13:36
  • One would think that with the publication of "Introduction to VLSI Design", by Mead and Conway at the beginning of the '80's, there would have been a shift towards more automated layout.
    – chthon
    Mar 23 at 16:15
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    @chthon Automated chip layout presupposes you have a powerful enough computer already to run a layout algorithm on a circuit more complex than itself. Acorn did not, so they did what was feasible on the computer, and the rest by hand.
    – Chromatix
    Mar 23 at 17:56
  • @airman I added a couple of notes on the choice of adder.
    – Chromatix
    Mar 23 at 17:56
  • "including the preparation of photolithography masks using a scalpel and a steady hand" -- as celebrated in the classic Rubylith of Omar Khyyam Mar 23 at 22:23
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(Partially) answering my own question, as I found an interesting resource about reverse engineering of vintage chips, using key words from Chromatix's answer.

One of the articles on the reverse engineering of the 8086: http://www.righto.com/2020/08/latches-inside-reverse-engineering.html

EDIT: for people like me who are more interested with actual answers than with deciding if questions are "focused" enough, here's an additional resource I found useful, but for NMOS only apparently: Introduction to VLSI Systems

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  • Yep, I've been reading that site for about two weeks. Lots of reverse-engineering of old computer chips. Good stuff.
    – DrSheldon
    Mar 23 at 18:37

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